參數(shù)資料
型號： AFE7222IRGCR
廠商： Texas Instruments
文件頁數(shù)： 25/106頁
文件大?。?/td> 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
TX_CMIX_SYNC_SRC – Specifies the sync source for TX CMIX. When cleared, SYNC pin is used as the
sync source. When set, a rising edge on serial interface bit TX_CMIX_SER_IF_SYNC in Register 0x10D
is used as the sync source for TX CMIX. This is applicable when TX_GLOBAL_SYNC_DIS is set and
TX_CMIX_SYNC_DIS is cleared.
VALUE
SYNC SOURCE
0
Pin
1
Serial interface bit
Register Name – CONFIG7 – Address 0x10C, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_GLOBAL_
TX_QMC_GAIN_PH_
TX_QMC_OFF_SYNC_ TX_DIV_SYNC_
TX_FIFO_SYNC_
SYNC_SRC
SRC
TX_FIFO_SYNC_SRC
–
Specifies
the
Sync
source
for
TX
FIFO.
It
is
applicable
when
TX_GLOBAL_SYNC_DIS is set and TX_FIFO_SYNC_DIS is cleared.
VALUE
SYNC SOURCE
0
Pin
1
Serial interface bit
When the value programmed is 1, a rising edge on the serial interface bit TX_FIFO_SER_IF_SYNC in
register 0x10D is used as the sync source for the FIFO.
TX_DIV_SYNC_SRC – Specifies the sync source for TX Divider. When cleared, SYNC pin is used as the
sync source. When set, a rising edge on serial interface bit TX_DIV_SER_IF_SYNC in register 0x10D is
used as the sync source for TX Divider. This is applicable when TX_GLOBAL_SYNC_DIS is set and
TX_DIV_SYNC_DIS is cleared.
TX_QMC_OFF_SYNC_SRC – Specifies the sync source for TX QMC Offset Correction. When cleared,
SYNC pin is used as the sync source. When set, a rising edge on serial interface bit
TX_QMC_OFF_SER_IF_SYNC in register 0x10D is used as the sync source for TX QMC Offset
Correction. This is applicable when TX_GLOBAL_SYNC_DIS is set and TX_QMC_OFF_SYNC_DIS is
cleared.
TX_QMC_GAIN_PH_SYNC_SRC – Specifies the sync source for TX QMC Gain Phase Correction. When
cleared, SYNC pin is used as the sync source. When set, a rising edge on serial interface bit
TX_QMC_GAIN_PH_SER_IF_SYNC in register 0x10D is used as the sync source for TX QMC Gain
Phase
Correction.
This
is
applicable
when
TX_GLOBAL_SYNC_DIS
is
set
and
TX_QMC_GAIN_PH_SYNC_DIS is cleared.
TX_GLOBAL_SYNC_SRC
–
Specifies
the
sync
source
for
TX.
This
is
applicable
when
TX_GLOBAL_SYNC_DIS is cleared.
VALUE
SYNC SOURCE
0
All blocks synced from the SYNC pin
1
All blocks synced using serial Interface bit
When serial interface is specified to be the sync source, a rising edge on the serial interface bit
TX_GLOB_SER_IF_SYNC in register 0x10D is used as the sync source.
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
25
Product Folder Link(s): AFE7222 AFE7225
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