參數(shù)資料
型號(hào): ADV7183BBSTZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 55/100頁(yè)
文件大?。?/td> 0K
描述: IC VIDEO DECODER NTSC 80-LQFP
產(chǎn)品培訓(xùn)模塊: Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝: 1
類型: 視頻解碼器
應(yīng)用: 投影儀,錄音機(jī),安全
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 788 (CN2011-ZH PDF)
ADV7183B
Rev. B | Page 58 of 100
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[7:6]
Table 76. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
Description
00 (default)
3 Xtal periods
01
15 Xtal periods
10
63 Xtal periods
11
Active until cleared
When the active until cleared interrupt duration is selected and
the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
For example, if the ADV7183B loses lock, an interrupt is
generated and INTRQ pin goes low. If the ADV7183B returns
to the locked state, INTRQ continues to drive low until the
SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
The ADV7183B resets with open drain enabled and all
interrupts masked off. Therefore, INTRQ is in a high
impedance state after reset. 01 or 10 has to be written to
INTRQ_OP_SEL[1:0] for a logic level to be driven out from the
INTRQ pin.
It is also possible to write to a register in the ADV7183B that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[1:0]
Table 77. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
Description
00 (default)
Open drain
01
Drive low when active
10
11
Drive high when active
Reserved
Multiple Interrupt Events
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7183B will not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits, as more than one can be active.
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as shown in this section.
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection
Bits Address 0x40 (Interrupt Space)[5:4]
Table 78. MV_INTRQ_SEL
MV_INTRQ_SEL[1:0]
Description
00
Reserved
01 (default)
Pseudo sync only
10
11
Color stripe only
Either pseudo sync or color stripe
Additional information relating to the interrupt system is
detailed in
255H
Table 84.
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