參數(shù)資料
型號(hào)： ADV7180
廠商： Analog Devices, Inc.
英文描述： 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述： 10位，4個(gè)采樣標(biāo)清視頻解碼器
文件頁(yè)數(shù)： 72/112頁(yè)
文件大?。?/td> 1320K
代理商： ADV7180
ADV7180
PIXEL PORT CONFIGURATION
The ADV7180 has a very flexible pixel port that can be
configured in a variety of formats to accommodate downstream
ICs. Table 96, Table 97, and Table 98 summarize the various
functions that the ADV7180 pins can have in different modes of
operation.
The ordering of components, for example, Cr vs. Cb for
Channels A, B, and C can be changed. Refer to the SWPC, Swap
Pixel Cr/Cb, Address 0x27 [7] section. Table 96 indicates the
default positions for the Cr/Cb components.
OF_SEL[3:0], Output Format Selection, Address 0x03 [5:2]
The modes in which the ADV7180 pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 98 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data rate
of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin
stays at the higher rate of 27 MHz. For information on outputting
the nominal 13.5 MHz clock on the LLC1 pin, see the section
LLC_PAD_SEL[2:0], LLC1 Output Selection,
Address 0x8F [6:4].
Rev. A | Page 72 of 112
SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
LLC_PAD_SEL[2:0], LLC1 Output Selection,
Address 0x8F [6:4]
The following I
2
C write allows the user to select between LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the OF_SEL[3:0], Output Format
Selection, Address 0x03 [5:2] section for additional information.
The LLC2 signal and data on the data bus are synchronized.
By default, the rising edge of LLC1/LLC2 is aligned with the
Y data; the falling edge occurs when the data bus holds C data.
The polarity of the clock, and therefore the Y/C assignments to
the clock edges, can be altered by using the polarity LLC pin.
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC1 pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC2 pin.
Table 96. ADV7180 LQFP-64 P15 to P0 Output/Input Pin Mapping
Format and Mode
15
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Data Port Pins P[15:0]
9
8
14
13
12
11
10
7
6
5
4
3
2
1
0
YCrCb[7:0]OUT
Y[7:0]OUT
CrCb[7:0]OUT
Table 97. ADV7180 LFCSP-40 P7 to P0 Output/Input Pin Mapping
Format and Mode
Video Out, 8-Bit, 4:2:2
Data Port Pins P[7:0]
4
YCrCb[7:0]OUT
7
6
5
3
2
1
0
Table 98. ADV7180 Standard Definition Pixel Port Modes
OF_SEL[3:0]
0000 to 0001
0010
0011 (Default)
0100 to 1111
Format
Reserved
16-bit @ LLC2 4:2:2
8-bit @ LLC1 4:2:2 (default)
Reserved
ADV7180 LQFP-64 P[15: 0]
P[15:8]
ADV7180 LFCSP-40
P[7: 0]
P[7: 0]
Reserved, do not use
CrCb[7:0]
Three-state
Reserved, do not use
Y[7:0]
YCrCb[7:0]
Not valid
YCrCb[7:0]
相關(guān)PDF資料
PDF描述
ADV7180BCPZ 10-Bit, 4 x Oversampling SDTV Video Decoder
ADV7180BSTZ 10-Bit, 4 x Oversampling SDTV Video Decoder
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7180_12 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 4?? Oversampling SDTV Video Decoder
ADV7180BCP32Z 制造商:Analog Devices 功能描述:10-BIT, 4? OVERSAMPLING SDTV VIDEO DECODER - Trays
ADV7180BCP32Z-RL 制造商:Analog Devices 功能描述:IC
ADV7180BCPZ 功能描述:IC VIDEO DECODER SDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND
ADV7180BCPZ 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40
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