參數(shù)資料
型號(hào): ADV7180
廠商: Analog Devices, Inc.
英文描述: 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述: 10位,4個(gè)采樣標(biāo)清視頻解碼器
文件頁(yè)數(shù): 60/112頁(yè)
文件大?。?/td> 1320K
代理商: ADV7180
ADV7180
CGMS and WSS
The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC, so the CGMS and WSS readback registers
are shared. WSS is biphase coded; the VDP does a biphase
decoding to produce the 14 raw WSS bits in the CGMS/WSS
readback I
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78 [2],
User Sub Map, Write Only, Self-Clearing
1—Reinitializes the CGMS/WSS readback registers.
Rev. A | Page 60 of 112
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78 [2],
User Sub Map, Read Only
0—CGMS/WSS was not detected.
1—CGMS/WSS was detected.
CGMS_WSS_DATA_0[3:0], Address 0x7D [3:0];
CGMS_WSS_DATA_1[7:0], Address 0x7E [7:0];
CGMS_WSS_DATA_2[7:0], Address 0x7F [7:0];
User Sub Map, Read Only
These bits hold the decoded CGMS or WSS data.
Refer to Figure 43 and Figure 44 for the I
2
C to WSS and CGMS
bit mapping.
2
C registers and to set the CGMS_WSS_AVL bit.
0
VIDEO
VDP_CGMS_WSS_
DATA_1[5:0]
VDP_CGMS_WSS_DATA_2
SRUN-IN
START
CODE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
11.0μs
38.4μs
42.5μs
Figure 43. WSS Waveform
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
VDP_CGMS_WSS_DATA_1
VDP_CGMS_WSS_
DATA_0[3:0]
VDP_CGMS_WSS_DATA_2
REF
+100 IRE
+70 IRE
0 IRE
–40 IRE
11.2μs
49.1μs ± 0.5μs
CRC SEQUENCE
2.235μs ± 20ns
Figure 44. CGMS Waveform
Table 77. CGMS Readback Registers
1
Signal Name
CGMS_WSS_DATA_0[3:0]
CGMS_WSS_DATA_1[7:0]
CGMS_WSS_DATA_2[7:0]
1
The register is a readback register; default value does not apply.
Register Location
VDP_CGMS_WSS_DATA_0[3:0]
VDP_CGMS_WSS_DATA_1[7:0]
VDP_CGMS_WSS_DATA_2[7:0]
Address (User Sub Map)
125
126
127
0x7D
0x7E
0x7F
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