參數(shù)資料
型號(hào)： ADV212-HD-EB
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADV212-HD
標(biāo)準(zhǔn)包裝： 1
主要目的： 視頻，視頻處理
嵌入式： 是，F(xiàn)PGA / CPLD
已用 IC / 零件： ADV212-HD
主要屬性： 與 1080i 和 720p SDI 兼容，32/64 位，33/66 MHz PCI 卡
次要屬性： GUI，JPEG2000 視頻編解碼器
已供物品： 板
相關(guān)產(chǎn)品： ADV212BBCZRL-150DKR-ND - IC CODEC VID JPEG 2000 144CSPBGA
ADV212BBCZRL-115DKR-ND - IC CODEC VID JPEG 2000 121CSPBGA
ADV212BBCZRL-150CT-ND - IC CODEC VID JPEG 2000 144CSPBGA
ADV212BBCZRL-115CT-ND - IC CODEC VID JPEG 2000 121CSPBGA
ADV212BBCZRL-150TR-ND - IC CODEC VID JPEG 2000 144CSPBGA
ADV212BBCZRL-115TR-ND - IC CODEC VID JPEG 2000 121CSPBGA
ADV212BBCZ-150-ND - IC CODEC VID JPEG 2000 144CSPBGA
ADV212BBCZ-115-ND - IC CODEC VID JPEG 2000 121CSPBGA
ADV212
Rev. B | Page 30 of 44
PLL REGISTERS
The ADV212 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 s before reading from or writing
to another register. If this delay is not implemented, erratic
behavior may result.
MCLK is the input clock to the ADV212 PLL and is used to
generate the internal JCLK (JPEG2000 processor clock) and
HCLK (embedded CPU clock).
The PLL can be programmed to have any possible final
multiplier value as long as
JCLK > 50 MHz and < 150 MHz (144-pin version).
JCLK > 50 MHz and < 115 MHz (121-pin version).
HCLK < 81 MHz (121-pin version) or HCLK < 108 MHz
(144-pin version).
JCLK ≥ 2 × VCLK for single-component input.
JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input.
In JDATA mode (JDATA), JCLK must be 4 × MCLK
or higher.
The maximum burst frequency for external DMA modes is
≤ 0.36 JCLK.
For MCLK frequencies greater than 50 MHz, the input
clock divider must be enabled; that is, IPD must be set
to 1. IPD cannot be enabled for MCLK frequencies
below 20 MHz.
Deinterlace modes require JCLK ≥ 4 × MCLK.
It is not recommended to use an LLC output from a video
decoder as a clock source for MCLK.
To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR 656
input. The PLL circuit is recommended to have a multiplier of
3. This sets JCLK and HCLK to 81 MHz.
LPF
PHASE
DETECT
VCO
JCLK
HCLK
÷2
HCLKD
÷PLLMULT
÷2
LFB
÷2
IPD
BYPASS
MCLK
06389-
009
Figure 32. PLL Architecture and Control Functions
Table 20. Recommended PLL Register Settings
IPD
LFB
PLLMULT
HCLKD
HCLK
JCLK
0
N
0
N × MCLK
0
N
1
N × MCLK/2
N × MCLK
0
1
N
0
2 × N × MCLK
0
1
N
1
N × MCLK
2 × N × MCLK
1
0
N
0
N × MCLK/2
1
0
N
1
N × MCLK/4
N × MCLK/2
1
N
0
N × MCLK
1
N
1
N × MCLK/2
N × MCLK
Table 21. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
CLKIN Frequency on MCLK
PLL_HI
PLL_LO
SMPTE 125M or ITU-R BT.656 (NTSC or PAL)
27 MHz
0x0008
0x0004
SMPTE 293M (525p)
27 MHz
0x0008
0x0004
ITU-R BT.1358 (625p)
27 MHz
0x0008
0x0004
SMPTE 274M (1080i)
74.25 MHz
0x0008
0x0084
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