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參數(shù)資料
| 型號(hào)： | ADV212-HD-EB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADV212-HD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 是，F(xiàn)PGA / CPLD |
| 已用 IC / 零件： | ADV212-HD |
| 主要屬性： | 與 1080i 和 720p SDI 兼容，32/64 位，33/66 MHz PCI 卡 |
| 次要屬性： | GUI，JPEG2000 視頻編解碼器 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV212BBCZRL-150DKR-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZRL-115DKR-ND - IC CODEC VID JPEG 2000 121CSPBGA ADV212BBCZRL-150CT-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZRL-115CT-ND - IC CODEC VID JPEG 2000 121CSPBGA ADV212BBCZRL-150TR-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZRL-115TR-ND - IC CODEC VID JPEG 2000 121CSPBGA ADV212BBCZ-150-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZ-115-ND - IC CODEC VID JPEG 2000 121CSPBGA |
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ADV212
Rev. B | Page 21 of 44
121-Ball Package
144-Ball Package
Pin No.
Location
Pin No.
Location
Mnemonic
Pins
Used
Type
Description
85
H8
83
G11
ACK
1
O
Acknowledge. Used for direct register accesses.
This signal indicates that the last register access
was successful. Due to synchronization issues,
control and status register accesses may incur an
additional delay; therefore, the host software
should wait for acknowledgment from the
ADV212 before attempting another register
access.
Accesses to the FIFOs (external DMA modes),
on the other hand, are guaranteed to occur
immediately, provided that space is available;
therefore, the host software does not need to
wait for ACK before attempting another register
access, provided that the timing constraints
are observed.
If ACK is shared with more than one device, ACK
should be connected to a pull-up resistor (10 k )
and the PLL_HI register, Bit 4, must be set to 1.
76
G10
82
G10
IRQ
1
O
Interrupt. This pin indicates that the ADV212
requires the attention of the host processor.
This pin can be programmed to indicate the
status of the internal interrupt conditions
within the ADV212. The interrupt sources are
enabled via the bits in the EIRQIE register.
63
F8
72
F12
DREQ0
1
O
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 0.
FSRQ0
O
FIFO Service Request. Used in DCS-DMA
mode. Service request from the FIFO assigned
to Channel 0 (asynchronous mode).
VALID
O
Valid Indication for JDATA Input/Output Stream.
Polarity of this pin is programmable in the
EDMOD0 register. VALID is always an output.
CFG1
I
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be
tied to IOVDD through a 10 k resistor.
64
F9
71
F11
DACK0
1
I
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ0) has been
acknowledged and that the data transfer can
proceed. This pin must be held high at all
times if the DMA interface is not used, even if
the DMA channels are disabled.
HOLD
I
External Hold Indication for JDATA Input/Output
Stream. Polarity is programmable in the
EDMOD0 register. This pin is always an input.
FCS0
I
FIFO Chip Select. Used in DCS-DMA mode.
Chip select for the FIFO assigned to Channel 0
(asynchronous mode).
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