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參數(shù)資料
| 型號： | ADV212-HD-EB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADV212-HD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 是，F(xiàn)PGA / CPLD |
| 已用 IC / 零件： | ADV212-HD |
| 主要屬性： | 與 1080i 和 720p SDI 兼容，32/64 位，33/66 MHz PCI 卡 |
| 次要屬性： | GUI，JPEG2000 視頻編解碼器 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV212BBCZRL-150DKR-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZRL-115DKR-ND - IC CODEC VID JPEG 2000 121CSPBGA ADV212BBCZRL-150CT-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZRL-115CT-ND - IC CODEC VID JPEG 2000 121CSPBGA ADV212BBCZRL-150TR-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZRL-115TR-ND - IC CODEC VID JPEG 2000 121CSPBGA ADV212BBCZ-150-ND - IC CODEC VID JPEG 2000 144CSPBGA ADV212BBCZ-115-ND - IC CODEC VID JPEG 2000 121CSPBGA |
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ADV212
Rev. B | Page 23 of 44
121-Ball Package
144-Ball Package
Pin No.
Location
Pin No.
Location
Mnemonic
Pins
Used
Type
Description
101
K2
122
L2
SCOMM3
I
Serial Communication. For internal use only.
This pin should be tied low via a 10 k
resistor.
115
L5
123
L3
SCOMM2
O
Serial Communication. For internal use only.
This pin should be tied low via a 10 k
resistor.
103
K4
109
K1
SCOMM1
I
Serial Communication. For internal use only.
This pin should be tied low via a 10 k
resistor.
102
K3
110
K2
SCOMM0
O
Serial Communication. This pin should be tied
low via a10 k resistor.
53
E9
60
E12
VCLK
1
I
Video Data Clock. This pin must be supplied if
video data is input/output on the VDATA bus.
44, 43, 29,
31, 32, 18
to 20, 22,
21, 7, 10
D11, D10,
C7, C9, C10,
B7, B8, B9,
B11, B10,
A7, A10
46 to 48,
34 to 36,
22 to 24,
9 to 11
D10 to D12,
C10 to C12,
B10 to B12,
A9 to A11
VDATA[11:0]
12
I/O
Video Data. Unused pins should be pulled
down via a 10 k resistor.
41
D8
58
E10
VSYNC
1
I/O
Vertical Sync for Video Mode.
VFRM
Raw Pixel Mode Framing Signal. When this pin
is asserted high, it indicates the first sample of
a tile.
42
D9
59
E11
HSYNC
1
I/O
Horizontal Sync for Video Mode.
VRDY
O
Raw Pixel Mode Ready Signal.
54
E10
57
E9
FIELD
1
I/O
Field Sync for Video Mode.
VSTRB
I
Raw Pixel Mode Transfer Strobe.
94
J6
120
K12
TCK
1
I
JTAG Clock. If not used, this pin should be
connected to ground via a pull-down resistor.
108
K9
119
K11
TRS
1
I
JTAG Reset. If the JTAG is used, this pin must
be toggled low to high. If JTAG is not used,
this pin must be held low.
98
J10
118
K10
TMS
1
I
JTAG Mode Select. If JTAG is used, connect a
10 k pull-up resistor to this pin. If not used,
this pin should be connected to ground via
a pull-down resistor.
116
L6
141
M9
TDI
1
I
JTAG Serial Data Input. If JTAG is used, connect
a 10 k pull-up resistor to this pin. If JTAG is
not used, this pin should be connected to
ground via a pull-down resistor.
109
K10
130
L10
TDO
1
O
JTAG Serial Data Output. If this pin is not used,
do not connect it.
3, 8, 40, 84,
120
A3, A8, D7,
H7, L10
18, 19, 30,
31, 42, 43,
102, 103,
114, 115,
126, 127,
142
B6, B7, C6,
C7, D6, D7,
J6, J7, K6,
K7, L6, L7,
M10
VDD
5/13
V
Positive Supply for Core.
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