參數(shù)資料
型號(hào)： ADV212-HD-EB
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/44頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR ADV212-HD
標(biāo)準(zhǔn)包裝： 1
主要目的： 視頻，視頻處理
嵌入式： 是，F(xiàn)PGA / CPLD
已用 IC / 零件： ADV212-HD
主要屬性： 與 1080i 和 720p SDI 兼容，32/64 位，33/66 MHz PCI 卡
次要屬性： GUI，JPEG2000 視頻編解碼器
已供物品： 板
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ADV212BBCZ-115-ND - IC CODEC VID JPEG 2000 121CSPBGA
ADV212
Rev. B | Page 22 of 44
121-Ball Package
144-Ball Package
Pin No.
Location
Pin No.
Location
Mnemonic
Pins
Used
Type
Description
65
F10
70
F10
DREQ1
1
O
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 1.
FSRQ1
O
FIFO Service Request. Used in DCS-DMA
mode. Service request from the FIFO assigned
to Channel 1 (asynchronous mode).
CFG2
I
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be
tied to DGND through a 10 k resistor.
75
G9
69
F9
DACK1
1
I
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed.
This pin must be held high at all times unless
a DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA
interface is not used, even if the DMA
channels are disabled.
FCS1
I
FIFO Chip Select. Used in DCS-DMA mode.
Chip select for the FIFO assigned to Channel 1
(asynchronous mode).
90 to 92, 78
J2 to J4, H1
111, 97 to
99
K3, J1 to J3
HDATA[31:28]
4
I/O
Host Expansion Bus.
JDATA[7:4]
I/O
JDATA Bus (JDATA Mode).
79 to 81, 70
H2 to H4, G4
100, 85 to
87
J4, H1 to H3
HDATA[27:24]
4
I/O
Host Expansion Bus.
JDATA[3:0]
I/O
JDATA Bus (JDATA Mode).
69, 68,
59, 58
G3, G2,
F4, F3
88, 73 to 75
H4, G1 to G3
HDATA[23:20]
4
I/O
Host Expansion Bus.
57, 46 to 48
F2, E2, E3,
E4
76, 61 to 63
G4, F1 to F3
HDATA[19:16]
4
I/O
Host Expansion Bus.
VDATA[15:12]
I/O
Video Data. Used only for raw pixel video
mode. Unused pins should be pulled down via
a 10 k resistor.
112
L2
134
M2
SCOMM7
8
I/O
Serial Communication. For internal use only.
This pin should be tied low via a 10 k
resistor.
113
L3
135
M3
SCOMM6
I/O
Serial Communication. For internal use only.
This pin should be tied low via a 10 k
resistor.
114
L4
136
M4
SCOMM5
I/O
Serial Communication. This pin must be used
in multiple chip mode to align the outputs of
two or more ADV212s. For details, see the
used, this pin should be tied low via a 10 k
resistor.
100
K1
121
L1
SCOMM4
O
LCODE Output in Encode Mode. When LCODE
is enabled, the output on this pin indicates on
a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit
interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled
by default.
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