參數(shù)資料
型號: ADUC836BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 53/80頁
文件大?。?/td> 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 7x16b; D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
ADuC836
–56–
ADuC836
–57–
SCON
UART Serial Port Control Registers
SFR Address
98H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXX. SCON SFR Bit Designations
Bit
Name
Description
7
SM0
UART Serial Mode Select Bits.
6
SM1
These bits select the Serial Port operating mode as follows:
SM0
SM1
Selected Operating Mode
0
Mode 0: Shift Register, fixed baud rate (fCORE/12)
0
1
Mode 1: 8-bit UART, variable baud rate
1
0
Mode 2: 9-bit UART, fixed baud rate (fCORE/64) or (fCORE/32)
1
Mode 3: 9-bit UART, variable baud rate
5
SM2
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if
SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon
as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth
data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received.
4
REN
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
3
TB8
Serial Port Transmit (Bit 9).
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
2
RB8
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
1
TI
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
TI must be cleared by user software.
0
RI
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
RI must be cleared by software.
UART SERIAL INTERFACE
The serial port is full-duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can com-
mence reception of a second byte before a previously received byte
has been read from the receive register. However, if the first byte
still has not been read by the time reception of the second byte is
complete, the first byte will be lost.The physical interface to the
serial data network is via pins RxD(P3.0) and TxD(P3.1), while
the SFR interface to the UART comprises the following registers:
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H).Writing to SBUF
loads the transmit register, and reading SBUF accesses a physi-
cally separate receive register.
UART OPERATING MODES
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RxD.TxD
outputs the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line.The 8 bits are transmitted
with the least significant bit (LSB) first, as shown in Figure 54.
Reception is initiated when the Receive Enable bit (REN) is 1 and
the Receive Interrupt bit (RI) is 0.When RI is cleared, the data
is clocked into the RxD line and the clock pulses are output from
the TxD line.
CORE
CLK
ALE
RxD
(DATA OUT)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
S6
S5
S4
S3
S2
S1
S6
S5
S4
S3
S2
S1
S6
S5
S4
S3
S2
S1
MACHINE
CYCLE 8
MACHINE
CYCLE 7
MACHINE
CYCLE 2
MACHINE
CYCLE 1
TxD
(SHIFT CLOCK)
Figure 54. UART Serial PortTransmission, Mode 0
REV. A
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