參數(shù)資料
型號(hào): ADUC836BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/80頁(yè)
文件大小: 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 62KB(62K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 7x16b; D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤(pán),CSP
包裝: 托盤(pán)
ADuC836
–12–
ADuC836
–13–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Pin No.
52-Lead 56-Lead
MQFP CSP
Mnemonic
Type* Description
40
43
EA
I/O
External Access Enable, Logic Input.When held high, this input enables the device to
fetch code from internal program memory locations 0000h to F7FFh.When held low,
this input enables the device to fetch all instructions from external program memory.
To determine the mode of code execution, i.e., internal or external, the EA pin is
sampled at the end of an external RESET assertion or as part of a device power cycle.
EA may also be used as an external emulation I/O pin, and therefore the voltage level
at this pin must not be changed during normal mode operation as it may cause an
emulation interrupt that will halt code execution.
41
44
PSEN
O
Program Store Enable, Logic Output.This output is a control signal that enables the
external program memory to the bus during external fetch operations. It is active every
six oscillator periods except during external data memory accesses.This pin remains
high during internal program execution. PSEN can also be used to enable Serial
Download mode when pulled low through a resistor at the end of an external RESET
assertion or as part of a device power cycle.
42
45
ALE
O
Address Latch Enable, Logic Output.This output is used to latch the low byte (and
page byte for 24-bit data address space accesses) of the address to external memory
during external code or data memory access cycles. It is activated every six oscillator
periods except during an external data memory access. It can be disabled by setting
the PCON.4 bit in the PCON SFR.
43–46
46–49
P0.0–P0.7
I/O
These pins are part of Port 0, which is an 8-bit, open-drain, bidirectional
49–52
52–55
(AD0–AD3)
I/O port. Port 0 pins that have 1s written to them float and in that state can be used
(AD4–AD7)as high impedance inputs. An external pull-up resistor will be required
on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed
low order address and data bus during accesses to external program or data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
*I = Input, O = Output, S = Supply.
REV. A
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