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| 型號： | ADUC836BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC836
–20–
ADuC836
–21–
SF (Sinc Filter Register)
The number in this register sets the decimation factor and thus
the output update rate for the primary and auxiliary ADCs.This
SFR cannot be written by user software while either ADC is active.
The update rate applies to both primary and auxiliary ADCs and
is calculated as follows:
f
SF
f
ADC
MOD
= ×
×
1
3
1
8
where:
fADC = ADC Output Update Rate
fMOD = Modulator Clock Frequency = 32.768 kHz
SF = Decimal Value of SF Register
The allowable range for SF is 0DH to FFH. Examples of SF
values and corresponding conversion update rates (fADC) and con-
version times (tADC) are shown in TableVIII.The power-on default
value for the SF Register is 45H, resulting in a default ADC update
rate of just under 20 Hz. Both ADC inputs are chopped to mini-
mize offset errors, which means that the settling time for a single
conversion, or the time to a first conversion result in Continuous
Conversion mode, is 2 tADC. As mentioned earlier, all calibra-
tion cycles will be carried out automatically with a maximum, i.e.,
FFH, SF value to ensure optimum calibration performance. Once
a calibration cycle has completed, the value in the SF Register will
be that programmed by user software.
Table VIII. SF SFR Bit Designations
SF(dec)
SF(hex)
fADC(Hz)
tADC(ms)
13
0D
105.3
9.52
69
45
19.79
50.34
255
FF
5.35
186.77
ICON (Current Sources Control Register)
The icon SFR is used to control and configure the various excitation and burnout current source options available on-chip.
SFR Address
D5H
Power-On Default Value
00H
Bit Addressable
No
Table IX. ICON SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
BO
Burnout Current Enable Bit.
Set by user to enable both transducer burnout current sources in the primary ADC signal paths.
Cleared by the user to disable both transducer burnout current sources.
5
ADC1IC
Auxiliary ADC Current Correction Bit. Set by user to allow scaling of the auxiliary ADC by an internal current
source calibration word.
4
ADC0IC
Primary ADC Current Correction Bit.
Set by user to allow scaling of the primary ADC by an internal current source calibration word.
3
I2PIN*
Current Source-2 Pin Select Bit.
Set by user to enable current source-2 (200 A) to external Pin 3 (P1.2/DAC/IEXC1).
Cleared by user to enable current source-2 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2).
2
I1PIN*
Current Source-1 Pin Select Bit.
Set by user to enable current source-1 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2).
Cleared by user to enable current source-1 (200 A) to external Pin 3 (P1.2/DAC/IEXC1).
1
I2EN
Current Source-2 Enable Bit.
Set by user to turn on excitation current source-2 (200 A).
Cleared by user to turn off excitation current source-2 (200 A).
0
I1EN
Current Source-1 Enable Bit.
Set by user to turn on excitation current source-1 (200 A).
Cleared by user to turn off excitation current source-1 (200 A).
*Both current sources can be enabled to the same external pin, yielding a 400 A current source.
REV. A
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