參數(shù)資料
型號： ADUC836BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/80頁
文件大小： 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 7x16b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC836
–30–
ADuC836
–31–
Flash/EE Program Memory
The ADuC836 contains a 64 Kbyte array of Flash/EE program
memory.The lower 62 Kbytes of this program memory are avail-
able to the user, and can be used for program storage or indeed
as additional NV data memory.
The upper 2 Kbytes of this Flash/EE program memory array con-
tain permanently embedded firmware, allowing in-circuit serial
download, serial debug, and nonintrusive single pin emulation.
These 2 Kbytes of embedded firmware also contain a power-on
configuration routine that downloads factory calibrated coeffi-
cients to the various calibrated peripherals (ADC, temperature
sensor, current sources, band gap references, and so on).
This 2 Kbyte embedded firmware is hidden from user code.
Attempts to read this space will read 0s, i.e., the embedded firm-
ware appears as NOP instructions to user code.
In normal operating mode (power-up default), the 62 Kbytes of
user Flash/EE program memory appear as a single block.This
block is used to store the user code, as shown in Figure 17.
FFFFH
0000H
F800H
F7FFH
USER PROGRAM MEMORY
62 KBYTES OF FLASH/EE PROGRAM MEMORY IS
AVAILABLE TO THE USER. ALL OF THIS SPACE CAN
BE PROGRAMMED FROM THE PERMANENTLY
EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN
PARALLEL PROGRAMMING MODE.
EMBEDDED DOWNLOAD/DEBUG KERNEL
PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE
TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF
ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM
APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE.
62 KBYTE
2 KBYTE
Figure 17. Flash/EE Program Memory Map in Normal Mode
In Normal mode, the 62 Kbytes of Flash/EE program memory
can be programmed by serial downloading or parallel processing:
(1) Serial Downloading (In-Circuit Programming)
The ADuC836 facilitates code download via the standard UART
serial port.The ADuC836 will enter Serial Download mode after
a reset or power cycle if the PSEN pin is pulled low through an
external 1 k resistor. Once in serial download mode, the hidden
embedded download kernel will execute.This allows the user to
download code to the full 62 Kbytes of Flash/EE program memo-
ry while the device is in circuit in its target application hardware.
A PC serial download executable is provided as part of the
ADuC836 QuickStart development system. Application Note
uC004 fully describes the serial download protocol that is used
by the embedded download kernel.This Application Note is
(2) Parallel Programming
The Parallel Programming mode is fully compatible with con-
ventional third party Flash or EEPROM device programmers.
A block diagram of the external pin configuration required to
support parallel programming is shown in Figure 18. In this mode,
Ports 0 and 2 operate as the external address bus interface, P3
operates as the external data bus interface, and P1.0 operates as
the Write Enable strobe. Port 1.1, P1.2, P1.3, and P1.4 are used
as a general configuration port that configures the device for vari-
ous program and erase operations during parallel programming.
Table XIII. Flash/EE Memory Parallel Programming Modes
Port 1 Pins
P1.4
P1.3
P1.2
P1.1
Programming Mode
0
Erase Flash/EE Program,
Data, and Security Modes
1
0
1
Read Device Signature/ID
1
0
1
0
Program Code Byte
0
1
0
Program Data Byte
1
0
1
Read Code Byte
0
1
Read Data Byte
1
0
Program Security Modes
1
0
1
Read/Verify Security Modes
All other codes
Redundant
VDD
GND
P1.1 -> P1.4
PSEN
RESET
P3
P0
P2
ADuC836
5V
PROGRAM MODE
(SEE TABLE XIII)
GND
PROGRAM
DATA
(D0–D7)
PROGRAM
ADDRESS
(A0–A13)
(P2.0 = A0)
(P1.7 = A13)
COMMAND
ENABLE
P1.0
EA
ENTRY
SEQUENCE
VDD
GND
P1.5 -> P1.7
TIMING
Figure 18. Flash/EE Memory Parallel Programming
REV. A
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