參數(shù)資料
型號： ADUC834BCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 60/80頁
文件大小： 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
REV. A
ADuC834
–63–
ADuC834 HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design consider-
ations that must be addressed when integrating the ADuC834
into any hardware system.
External Memory Interface
In addition to its internal program and data memories, the
ADuC834 can access up to 64 Kbytes of external program memory
(ROM/PROM/and so on) and up to 16 Mbytes of external data
memory (SRAM).
To select from which code space (internal or external program
memory) to begin executing code, tie the
EA (external access)
pin high or low, respectively. When
EA is high (pulled up to
VDD), user program execution will start at Address 0 in the
internal 62 Kbytes Flash/EE code space. When
EA is low (tied
to ground) user program execution will start at Address 0 in the
external code space. When executing from internal code space,
accesses to the program space above F7FFH (62 Kbytes) will be
read as NOP instructions.
Note that a second very important function of the
EA pin is
described in the Single Pin Emulation Mode section.
External program memory (if used) must be connected to
the ADuC834 as illustrated in Figure 58. Sixteen I/O lines
(Ports 0 and 2) are dedicated to bus functions during external
program memory fetches. Port 0 (P0) serves as a multiplexed
address/databus. It emits the low byte of the program counter
(PCL) as an address, and then goes into a high impedance input
state awaiting the arrival of the code byte from the program
memory. During the time that the low byte of the program counter
is valid on P0, the signal ALE (Address Latch Enable) clocks
this byte into an external address latch. Meanwhile, Port 2 (P2)
emits the high byte of the program counter (PCH), and
PSEN
strobes the EPROM and the code byte is read into the ADuC834.
LATCH
EPROM
OE
A8–A15
A0–A7
D0–D7
(INSTRUCTION)
ADuC834
PSEN
P2
ALE
P0
Figure 58. External Program Memory Interface
Note that program memory addresses are always 16 bits wide,
even in cases where the actual amount of program memory used
is less than 64 Kbytes. External program execution sacrifices two
of the 8-bit ports (P0 and P2) to the function of addressing the
program memory. While executing from external program memory,
Ports 0 and 2 can be used simultaneously for read/write access
to external data memory, but not for general-purpose I/O.
Though both external program memory and external data
memory are accessed using some of the same pins, the two are
completely independent of each other from a software point of
view. For example, the chip can read/write external data memory
while executing from external program memory.
Figure 59 shows a hardware configuration for accessing up to
64 Kbytes of external data memory. This interface is standard
to any 8051 compatible MCU.
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
ADuC834
RD
P2
ALE
P0
WE
WR
Figure 59. External Data Memory Interface
(64 Kbytes Address Space)
If access to more than 64 Kbytes of RAM is desired, a feature
unique to the MicroConverter allows addressing up to 16 Mbytes
of external RAM simply by adding an additional latch as illus-
trated in Figure 60.
LATCH
ADuC834
RD
P2
ALE
P0
WR
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
WE
A16–A23
Figure 60. External Data Memory Interface
(16 Mbytes Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/databus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by ALE prior to data being placed
on the bus by the ADuC834 (write operation) or the external
data memory (read operation). Port 2 (P2) provides the data
pointer page byte (DPP) to be latched by ALE, followed by the
data pointer high byte (DPH). If no latch is connected to P2,
DPP is ignored by the SRAM, and the 8051 standard of 64 Kbyte
external data memory access is maintained.
Detailed timing diagrams of external program and data memory
read and write access can be found in the Timing Specification
sections of this data sheet.
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