參數(shù)資料
型號： ADUC834BCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 16/80頁
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
REV. A
ADuC834
–23–
-
MODULATOR
PROGRAMMABLE
DIGITAL
FILTER
-
ADC
BUFFER
AGND
AV
DD
REFIN(–) REFIN(+)
CHOP
AIN1
AIN2
AIN3
AIN4
OUTPUT
AVERAGE
OUTPUT
SCALING
DIGTAL OUTPUT
RESULT WRITTEN
TO ADC0H/M/L
SFRS
PGA
CHOP
OUTPUT AVERAGE
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA-WORD OUTPUT
FROM THE FILTER IS
SUMMED AND AVERAGED
WITH ITS PREDECESSOR
TO NULL ADC CHANNEL
OFFSET ERRORS.
-
ADC
THE
-
ARCHITECTURE
ENSURES 24 BITS NO
MISSING CODES. THE
ENTIRE
-
ADC IS
CHOPPED TO REMOVE
DRIFT ERROR.
DIFFERENTIAL
REFERENCE
THE EXTERNAL REFERENCE
INPUT TO THE ADuC834 IS
DIFFERENTIAL AND
FACILITATES RATIOMETRIC
OPERATION. THE EXTERNAL
REFERENCE VOLTAGE IS
SELECTED VIA THE XREF0 BIT
IN ADC0CON.
REFERENCE DETECT
CIRCUITRY TESTS FOR OPEN OR
SHORTED REFERENCE INPUTS.
ANALOG INPUT CHOPPING
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE
CONVERSION CYCLE.
CHOPPING YIELDS
EXCELLENT ADC OFFSET
AND OFFSET DRIFT
PERFORMANCE.
BURNOUT CURRENTS
TWO 100nA BURNOUT
CURRENTS ALLOW THE
USER TO EASILY DETECT
IF A TRANSDUCER HAS
BURNED OUT OR GONE
OPEN-CIRCUIT.
ANALOG MULTIPLEXER
A DIFFERENTIAL MULTIPLEXER
ALLOWS SELECTION OF THREE
FULLY DIFFERENTIAL PAIR OPTIONS AND
ADDITIONAL INTERNAL SHORT OPTION
(AIN2–AIN2). THE MULTIPLEXER IS
CONTROLLED VIA THE CHANNEL
SELECTION BITS IN ADC0CON.
BUFFER AMPLIFIER
THE BUFFER AMPLIFIER
PRESENTS A HIGH
IMPEDANCE INPUT STAGE
FOR THE ANALOG INPUTS,
ALLOWING SIGNIFICANT
EXTERNAL SOURCE
IMPEDANCES.
THE MODULATOR PROVIDES
A HIGH FREQUENCY 1-BIT
DATA STREAM (THE OUTPUT
OF WHICH IS ALSO CHOPPED)
TO THE DIGITAL FILTER,
THE DUTY CYCLE OF WHICH
REPRESENTS THE SAMPLED
ANALOG INPUT VOLTAGE.
-
MODULATOR
PROGRAMMABLE
DIGITAL FILTER
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE
VIA THE SF SFR.
THE OUPUT WORD FROM THE
DIGITAL FILTER IS SCALED
BY THE CALIBRATION
COEFFICIENTS BEFORE
BEING PROVIDED AS
THE CONVERSION RESULT.
OUTPUT SCALING
PROGRAMMABLE GAIN
AMPLIFIER
THE PROGRAMMABLE
GAIN AMPLIFIER ALLOWS
EIGHT UNIPOLAR AND
EIGHT BIPOLAR INPUT
RANGES FROM 20mV TO
2.56V (EXT VREF = 2.5V).
MUX
PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC834 incorporates two independent - ADCs (primary
and auxiliary) with on-chip digital filtering intended for the measure-
ment of wide dynamic range, low frequency signals such as those
in weigh-scale, strain gage, pressure transducer, or temperature
measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of eight input
ranges from
± 20 mV to ± 2.56 V being driven from one of three
differential input channel options AIN1/2, AIN3/4, or AIN3/2.
The input channel is internally buffered, allowing the part to
handle significant source impedances on the analog input and
allowing R/C filtering (for noise rejection or RFI reduction) to be
placed on the analog inputs if required. On-chip burnout currents
can also be turned on. These currents can be used to check that
a transducer on the selected channel is still operational before
attempting to take measurements.
The ADC employs a
-
conversion technique to realize up to
24 bits of no missing codes performance. The - modulator con-
verts the sampled input signal into a digital pulse train whose duty
cycle contains the digital information. A Sinc
3 programmable low-
pass filter is then employed to decimate the modulator output data
stream to give a valid data conversion result at programmable
output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms).
A chopping scheme is also employed to minimize ADC offset errors.
A block diagram of the primary ADC is shown in Figure 7.
Figure 7. Primary ADC Block Diagram
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