參數(shù)資料
型號(hào)： ADUC834BCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 10/80頁
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
REV. A
–18–
ADuC834
ADCMODE (ADC Mode Register)
Used to control the operational mode of both ADCs.
SFR Address
D1H
Power-On Default Value
00H
Bit Addressable
No
Table V. ADCMODE SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
–––
Reserved for Future Use
5
ADC0EN
Primary ADC Enable.
Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0 below.
Cleared by the user to place the primary ADC in power-down mode.
4
ADC1EN
Auxiliary ADC Enable.
Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0 below.
Cleared by the user to place the auxiliary ADC in power-down mode.
3
–––
Reserved for Future Use
2
MD2
Primary and auxiliary ADC Mode bits.
1
MD1
These bits select the operational mode of the enabled ADC as follows:
0
MD0
MD2 MD1 MD0
0
00
ADC Power-Down Mode (Power-On Default)
0
01
Idle Mode. In Idle Mode, the ADC filter and modulator are held in a reset state
although the modulator clocks are still provided.
0
10
Single Conversion Mode. In Single Conversion Mode, a single conversion is
performed on the enabled ADC. On completion of the conversion, the ADC data
registers (ADC0H/M/L and/or ADC1H/L) are updated, the relevant flags in the
ADCSTAT SFR are written, and power-down is re-entered with the MD2–MD0
accordingly being written to 000.
0
11
Continuous Conversion. In Continuous Conversion Mode, the ADC data registers
are regularly updated at the selected update rate (see SF Register).
1
00
Internal Zero-Scale Calibration. Internal short automatically connected to the
enabled ADC input(s).
1
01
Internal Full-Scale Calibration Internal or External VREF (as determined by
XREF0 and XREF1 bits in ADC0/1CON) is automatically connected to the
enabled ADC input(s) for this calibration.
1
10
System Zero-Scale Calibration. User should connect system zero-scale input to
the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in
the ADC0/1CON Register.
1
11
System Full-Scale Calibration. User should connect system full-scale input to
the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the
ADC0/1CON Register.
NOTES
1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 Bits with no change is also treated as a reset. (See exception to this in Note 3 below.)
2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC
is given priority over the auxiliary ADC and any change requested on the primary ADC is immediately responded to.
3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously
converting when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase
difference from the primary ADC, the auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the
auxiliary ADC will be delayed up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC.
4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion,
the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in
power-down mode.
5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the
calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set.
6. Calibrations are performed at maximum SF (see SF SFR) value guaranteeing optimum calibration operation.
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