參數(shù)資料
型號： ADUC834BCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 39/80頁
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝： 2,500
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
REV. A
–44–
ADuC834
SERIAL PERIPHERAL INTERFACE
The ADuC834 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full
duplex. It should be noted that the SPI pins SCLOCK and MOSI
are multiplexed with the I
2C pins SCLOCK and SDATA. The
pins are controlled via the I2CCON SFR only if SPE is clear.
SPI can be configured for master or slave operation and typically
consists of four pins, namely:
SCLOCK (Serial Clock I/O Pin), Pin 26
The master clock (SCLOCK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is configured as an
output in master mode and as an input in Slave mode. In master
mode the bit-rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XXI). In Slave mode the SPICON register will have to
be configured with the phase and polarity (CPHA and CPOL) as
the master as for both Master and Slave mode the data is transmitted
on one edge of the SCLOCK signal and sampled on the other.
MISO (Master In, Slave Out Data I/O Pin), Pin 14
The MISO (master in slave out) pin is configured as an input
line in Master mode and an output line in Slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin 27
The MOSI (master out slave in) pin is configured as an output
line in Master mode and an input line in Slave mode. The MOSI
line on the master (data out) should be connected to the MOSI line
in the slave device (data in). The data is transferred as byte-wide
(8-bit) serial data, MSB first.
SS (Slave Select Input Pin), Pin 13
The Slave Select (
SS) input pin is only used when the ADuC834
is configured in SPI Slave mode. This line is active low. Data is only
received or transmitted in Slave mode when the
SS pin is low,
allowing the ADuC834 to be used in single master, multislave SPI
configurations. If CPHA = 1, the
SS input may be permanently
pulled low. With CPHA = 0, the
SS input must be driven low
before the first bit in a byte wide transmission or reception and
return high again after the last bit in that byte wide transmission
or reception. In SPI Slave mode, the logic level on the external
SS pin (Pin 13), can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
Table XXI. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR
6
WCOL
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
2C interface.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by user to enable Master mode operation (SCLOCK is an output).
Cleared by user to enable Slave mode operation (SCLOCK is an input).
3
CPOL
*
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
2
CPHA
*
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
1
SPR1
SPI Bit-Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bit-rate) in Master mode as follows:
SPR1
SPR0
Selected Bit Rate
00
fCORE/2
01
fCORE/4
10
fCORE/8
11
fCORE/16
In SPI Slave mode, i.e., SPIM = 0, the logic level on the external
SS pin (Pin 13), can be read
via the SPR0 bit.
*The CPOL and CPHA bits should both contain the same values for master and slave devices.
相關(guān)PDF資料
PDF描述
ADUC836BCPZ IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC843BSZ62-5 IC ADC 12BIT W/FLASH MCU 52-MQFP
ADUC845BCPZ62-5 IC FLASH MCU W/24BIT ADC 56-CSP
ADUC847BCPZ62-5 IC MCU FLASH W/24BIT ADC 56-CSP
ADV202BBCZ-135 IC CODEC VIDEO 135MHZ 144CSPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADUC834BS 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.58MHZ 3.3/5V 52MQFP - Bulk 制造商:Analog Devices 功能描述:8BIT MCU +24/16BIT ADC SMD MQFP52
ADUC834BSZ 功能描述:IC ADC DUAL16/24BIT W/MCU 52MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
ADUC836 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
ADUC836_02 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
ADUC836BCP 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*