參數(shù)資料
型號： ADUC7036CCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 127/132頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LFCSP
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC7036
Rev. C | Page 94 of 132
GPIO Port1 Clear Register
Name: GP1CLR
Address: 0xFFFF0D38
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP1CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP1DAT).
Table 69. GP1CLR MMR Bit Designations
Bit
Description
31 to 18
Reserved. These bits are reserved and should be written as 0 by user code.
17
Port 1.1 clear bit.
Set to 1 by user code to clear the external GPIO_6 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin.
16
Port 1.0 clear bit.
Set to 1 by user code to clear the external GPIO_5 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin.
15 to 0
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO Port2 Clear Register
Name: GP2CLR
Address: 0xFFFF0D48
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP2CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT).
Table 70. GP2CLR MMR Bit Designations
Bit
Description
31 to 23
Reserved. These bits are reserved and should be written as 0 by user code.
22
Port 2.6 clear bit.
Set to 1 by user code to clear the external GPIO_13 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
21
Port 2.5 clear bit.
Set to 1 by user code to clear the external GPIO_12 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
20 to 18
Reserved. These bits are reserved and should be written as 0 by user code.
17
Port 2.1 clear bit.
Set to 1 by user code to clear the external GPIO_8 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
16
Port 2.0 clear bit.
Set to 1 by user code to clear the external GPIO_7 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
15 to 0
Reserved. These bits are reserved and should be written as 0 by user code.
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