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參數(shù)資料
| 型號(hào)： | ADUC7036CCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 126/132頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 包裝： | 托盤(pán) |
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ADuC7036
Rev. C | Page 93 of 132
GPIO Port2 Set Register
Name: GP2SET
Address: 0xFFFF0D44
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this
using the GP2SET MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT).
Table 67. GP2SET MMR Bit Designations
Bit
Description
31 to 23
Reserved. These bits are reserved and should be written as 0 by user code.
22
Port 2.6 set bit.
Set to 1 by user code to set the external GPIO_13 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_13 pin.
21
Port 2.5 set bit.
Set to 1 by user code to set the external GPIO_12 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_12 pin.
20 to 18
Reserved. These bits are reserved and should be written as 0 by user code.
17
Port 2.1 set bit.
Set to 1 by user code to set the external GPIO_8 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
16
Port 2.0 set bit.
Set to 1 by user code to set the external GPIO_7 pin high.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
15 to 0
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO Port0 Clear Register
Name: GP0CLR
Address: 0xFFFF0D28
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP0CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP0DAT).
Table 68. GP0CLR MMR Bit Designations
Bit
Description
31 to 21
Reserved. These bits are reserved and should be written as 0 by user code.
20
Port 0.4 clear bit.
Set to 1 by user code to clear the external GPIO_4 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin.
19
Port 0.3 clear bit.
Set to 1 by user code to clear the external GPIO_3 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin.
18
Port 0.2 clear bit.
Set to 1 by user code to clear the external GPIO_2 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin.
17
Port 0.1 clear bit.
Set to 1 by user code to clear the external GPIO_1 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin.
16
Port 0.0 clear bit.
Set to 1 by user code to clear the external GPIO_0 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin.
15 to 0
Reserved. These bits are reserved and should be written as 0 by user code.
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