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參數(shù)資料
| 型號： | ADSP-BF547YBCZ-4A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP BLACKFIN 400MHZ 400CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | SPI，SSP，TWI，UART，USB |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 260kB |
| 電壓 - 輸入/輸出： | 2.50V，3.30V |
| 電壓 - 核心： | 1.25V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 400-CSPBGA（17x17） |
| 包裝： | 托盤 |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
|
Page 21 of 100
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May 2011
when the pre-boot has finished and the boot kernel starts the
boot process. However, the HWAIT signal does not toggle in
NAND boot mode. By programming OTP memory, the user
can instruct the preboot routine to also customize the PLL, volt-
age regulator, DDR controller, and/or asynchronous memory
interface controller.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass the pre-boot routine and/or boot
kernel in case of a software reset. They can also be used to simu-
late a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the DDR controller or to speed up booting by managing PLL,
clock frequencies, wait states, and/or serial bit rates.
The boot ROM also features C-callable function entries that can
be called by the user application at run time. This enables sec-
ond-stage boot or booting management schemes to be
implemented with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
The ADSP-BF54x Blackfin processors are supported with a
complete set of CROSSCORE software and hardware develop-
ment tools, including Analog Devices emulators and
VisualDSP++ development environment. The same emulator
hardware that supports other Blackfin processors also fully
emulates the ADSP-BF54x Blackfin processors.
EZ-KIT Lite Evaluation Board
For evaluation of ADSP-BF54x Blackfin processors, use the
ADSP-BF548 EZ-KIT Lite
board available from Analog
Devices. Order part number ADZS-BF548-EZLITE. The board
comes with on-chip emulation capabilities and is equipped to
enable software development. Multiple daughter cards are
available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. The emulator uses
the TAP to access the internal features of the processor, allow-
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor is
set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices web site under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
MXVR BOARD LAYOUT GUIDELINES
The MXVR Loop Filter RC network is connected between the
MLF_P and MLF_M pins in the following manner:
Capacitors:
C1: 0.047 μF (PPS type, 2% tolerance recommended)
C2: 330 pF (PPS type, 2% tolerance recommended)
Resistor:
R1: 330 Ω (1% tolerance)
The RC network should be located physically close to the
MLF_P and MLF_M pins on the board.
The RC network should be shielded using GNDMP traces.
Avoid routing other switching signals near the RC network to
avoid crosstalk.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADSP-BF548BBCZ | 制造商:Analog Devices 功能描述: |
| ADSP-BF548BBCZ-5A | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF548BBCZ-5AA | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA 制造商:analog devices inc. 系列:Blackfin? 包裝:托盤 零件狀態(tài):有效 類型:定點 接口:CAN，SPI，SSP，TWI，UART，USB 時鐘速率:533MHz 非易失性存儲器:外部 片載 RAM:260kB 電壓 - I/O:2.50V，3.30V 電壓 - 內(nèi)核:1.25V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:400-LFBGA，CSPBGA 供應(yīng)商器件封裝:400-CSPBGA（17x17） 標(biāo)準(zhǔn)包裝:1 |
| ADSP-BF548BBCZ-5X | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF548MBBCZ-5M | 功能描述:IC DSP 533MHZ W/DDR 400CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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