參數(shù)資料
型號: ADSP-21991BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 34/44頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 176-LQFP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點
接口: SPI,SSP
時鐘速率: 160MHz
非易失內(nèi)存: 外部
芯片上RAM: 112kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-LQFP(24x24)
包裝: 托盤
ADSP-21991
–4–
REV. 0
Efficient data transfer in the core is achieved with the use of
internal buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Direct Memory Access Address Bus
Direct Memory Access Data Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-21991 to fetch two operands in a single cycle, one
from program memory and one from data memory. The DSP
dual memory buses also let the embedded ADSP-219x core fetch
an operand from data memory and the next instruction from
program memory in a single cycle.
Memory Architecture
The ADSP-21991 provides 40K words of on-chip SRAM
memory. This memory is divided into three blocks: two
16K
× 24-bit blocks (blocks 0 and 1) and one 8K × 16-bit block
(block 2). In addition, the ADSP-21991 provides a 4K
× 24-bit
block of program memory boot ROM (that is reserved by ADI
for boot load routines). The memory map of the ADSP-21991
is illustrated in Figure 2.
As shown in Figure 2, the three internal memory RAM blocks
reside in memory page 0. The entire DSP memory map consists
of 256 pages (pages 0 to 255), and each page is 64K words long.
External memory space consists of four memory banks
(banks3–0) and supports a wide variety of memory devices. Each
bank is selectable using unique memory select lines (
MS3–0) and
has configurable page boundaries, wait states, and wait state
modes. The 4K words of on-chip boot ROM populates the top
of page 255, while the remaining 254 pages are addressable off-
chip. I/O memory pages differ from external memory in that they
are 1K word long, and the external I/O pages have their own select
pin (
IOMS). Pages 31–0 of I/O memory space reside on-chip and
Figure 1. Block Diagram
DATA
ADDRESS
B
L
O
C
K
3
DATA
ADDRESS
B
L
O
C
K
2
SYSTEM INTERRUPT
CONTROLLER
I/O DATA
I/O REGISTERS
(MEMORY-MAPPED)
CONTROL
STATUS
BUFFERS
I/O PROCESSOR
CACHE
64
24-BIT
JTAG
TEST AND
EMULATION
6
ADDR BUS
MUX
DATA BUS
MUX
16
20
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
PX
24
16
ADSP-219x DSP CORE
PROGRAM
SEQUENCER
DATA
REGISTER
FILE
MULT
BARREL
SHIFTER
ALU
DMA CONTROLLER
INPUT
REGISTERS
RESULT
REGISTERS
16
16-BIT
INTERNAL MEMORY
24
ADDRESS
B
L
O
C
K
1
DATA
ADDRESS
B
L
O
C
K
0
24 BIT
16 BIT
FOUR INDEPENDENT BLOCKS
PROGRAMMABLE
FLAGS (16)
TIMERS
(3)
3
DMA CONNECT
DMA ADDRESS
EXTERNAL PORT
24 BIT
18
I/O ADDRESS
24
16
24
DMA DATA
EMBEDDED
CONTROL
PERIPHERALS
AND
COMMUNICATIONS
PORTS
DAG1
4
16
DAG2
4
16
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