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| 型號： | ADSP-21991BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 176-LQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | SPI，SSP |
| 時鐘速率： | 160MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 112kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP（24x24） |
| 包裝： | 托盤 |
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ADSP-21991
–10–
REV. 0
The encoder interface unit can also be made to implement some
error checking functions. If an encoder count error is detected
(due to a disconnected encoder line, for example), a status bit in
the EIUSTAT register is set, and an EIU count error interrupt is
generated.
The encoder interface unit of the ADSP-21991 contains a 16-bit
loop timer that consists of a timer register, period register and
scale register so that it can be programmed to time out and reload
at appropriate intervals. When this loop timer times out, an EIU
loop timer timeout interrupt is generated. This interrupt could
be used to control the timing of speed and position control loops
in high performance drives.
The encoder interface unit also includes a high performance
encoder event timer (EET) block that permits the accurate timing
of successive events of the encoder inputs. The EET can be pro-
grammed to time the duration between up to 255 encoder pulses
and can be used to enhance velocity estimation, particularly at
low speeds of rotation.
Flag I/O (FIO) Peripheral Unit
The FIO module is a generic parallel I/O interface that supports
sixteen bidirectional multifunction flags or general-purpose
digital I/O signals (PF15–0).
All sixteen FLAG bits can be individually configured as an input
or output based on the content of the direction (DIR) register,
and can also be used as an interrupt source for one of two FIO
interrupts. When configured as input, the input signal can be
programmed to set the FLAG on either a level (level sensitive
input/interrupt) or an edge (edge sensitive input/interrupt).
The FIO module can also be used to generate an asynchronous
unregistered wake-up signal FIO_WAKEUP for DSP core wake
up after power-down.
The FIO Lines, PF7–1 can also be configured as external slave
select outputs for the SPI communications port, while PF0 can
be configured to act as a slave select input.
The FIO Lines can be configured to act as a PWM shutdown
source for the 3-phase PWM generation unit of the
ADSP-21991.
Watchdog Timer
The ADSP-21991 integrates a watchdog timer that can be used
as a protection mechanism against unintentional software events.
It can be used to cause a complete DSP and peripheral reset in
such an event. The watchdog timer consists of a 16-bit timer that
is clocked at the external clock rate (CLKIN or crystal input
frequency).
In order to prevent an unwanted timeout or reset, it is necessary
to periodically write to the watchdog timer register. During
abnormal system operation, the watchdog count will eventually
decrement to 0 and a watchdog timeout will occur. In the system,
the watchdog timeout will cause a full reset of the DSP core and
peripherals.
General-Purpose Timers
The ADSP-21991 contains a general-purpose timer unit that
contains three identical 32-bit timers. The three programmable
interval timers (Timer0, Timer1, and Timer2) generate periodic
interrupts. Each timer can be independently set to operate in one
of three modes:
Pulse Waveform Generation (PWM_OUT) mode
Pulsewidth Count/Capture (WDTH_CAP) mode
External Event Watchdog (EXT_CLK) mode
Each Timer has one bidirectional chip pin, TMR2-0. For each
timer, the associated pin is configured as an output pin in
PWM_OUT Mode and as an input pin in WDTH_CAP and
EXT_CLK Modes.
Interrupts
The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The DSP core implements an interrupt
priority scheme as shown in Table 2. Applications can use the
unassigned slots for software and peripheral interrupts. The
Peripheral Interrupt Controller is used to assign the various
peripheral interrupts to the 12 user assignable interrupts of the
DSP core.
Table 2. Interrupt Priorities/Addresses
Interrupt
IMASK/
IRPTL
Vector Address
Emulator (NMI)
—Highest Priority
NA
Reset (NMI)
0
0x00 0000
Power-Down (NMI)
1
0x00 0020
Loop and PC Stack
2
0x00 0040
Emulation Kernel
3
0x00 0060
User Assigned Interrupt
(USR0)
4
0x00 0080
User Assigned Interrupt
(USR1)
5
0x00 00A0
User Assigned Interrupt
(USR2)
6
0x00 00C0
User Assigned Interrupt
(USR3)
7
0x00 00E0
User Assigned Interrupt
(USR4)
8
0x00 0100
User Assigned Interrupt
(USR5)
9
0x00 0120
User Assigned Interrupt
(USR6)
10
0x00 0140
User Assigned Interrupt
(USR7)
11
0x00 0160
User Assigned Interrupt
(USR8)
12
0x00 0180
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| ADSP-21992BBC | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:MIXED SIGNAL DSP W/32K DM RAM& 16K PMRAM - Bulk |
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| ADSP-21992BSTZ | 功能描述:IC DSP CONTROLLER 16BIT 176LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21992YBC | 功能描述:IC DSP CTLR 16BIT 196CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21992YST | 制造商:Analog Devices 功能描述: |
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