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參數(shù)資料
| 型號： | ADSP-2173 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DSP Microcomputer(DSP 微計算機) |
| 中文描述： | 微機的DSP（數(shù)字信號處理器微計算機） |
| 文件頁數(shù)： | 6/52頁 |
| 文件大小： | 685K |
| 代理商： | ADSP-2173 |
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REV. A
–6–
ADSP-2171/ADSP-2172/ADSP-2173
LOW POWE R OPE RAT ION
T he ADSP-217x has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. T hese modes are:
Powerdown
Idle
Slow Idle
T he CLK OUT pin may also be disabled to reduce external
power dissipation. T he CLK OUT pin is controlled by Bit 14 of
SPORT 0 Autobuffer Control Register, DM[0x3FF3].
Powerdown
T he ADSP-217x processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of powerdown fea-
tures. Refer to the
ADSP-2100 Family User’s Manual
, Chapter 9
“System Interface” for detailed information about the
powerdown feature.
Powerdown mode holds the processor in CMOS standby with
a maximum current of less than 100
μ
A in some modes.
Quick recovery from powerdown. T he processor begins ex-
ecuting instructions in as few as 100 CLK IN cycles.
Support for an externally generated T T L or CMOS processor
clock. T he external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLK IN cycle recovery.
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLK IN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 100 CLK IN cycle startup.
Powerdown is initiated by either the powerdown pin (
PWD
)
or the software powerdown force bit.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. T he
powerdown interrupt also can be used as a non-maskable,
edge sensitive interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
powerdown state.
T he
RESET
pin also can be used to terminate powerdown,
and the host software reset feature can be used to terminate
powerdown under certain conditions.
Powerdown acknowledge pin indicates when the processor has
entered powerdown.
Idle
When the ADSP-217x is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the
IDLE
instruction.
Slow Idle
T he
IDLE
instruction is enhanced on the ADSP-217x to let the
processor’s internal clock signal be slowed during
IDLE
, further
reducing power consumption. T he reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the
IDLE
instruction. T he format of
the instruction is
IDLE (n);
where
n
= 16, 32, 64, or 128. T his instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK , CLK OUT , and timer clock, are reduced by the
same ratio. T he default form of the instruction, when no clock
divisor is given, is the standard
IDLE
instruction.
When the
IDLE (n)
instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts––the 1-cycle response time of the standard
idle state is increased by
n
, the clock divisor. When an enabled
interrupt is received, the ADSP-217x will remain in the idle
state for up to a maximum of
n
processor cycles (
n
= 16, 32, 64,
or 128) before resuming normal operation.
When the
IDLE (n)
instruction is used in systems that have an
externally generated serial clock (SCLK ), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of
n
processor cycles).
SY ST E M INT E RFACE
Figure 3 shows a basic system configuration with the ADSP-
217x, two serial devices, a host processor, a boot EPROM, and
optional external program and data memories. Up to 14K words
of data memory and 16K words of program memory can be sup-
ported. Programmable wait state generation allows the processor
to interface easily to slow memories. T he ADSP-217x also pro-
vides one external interrupt and two serial ports or three exter-
nal interrupts and one serial port.
Clock Signals
T he ADSP-217x can be clocked by either a crystal or by a T T L-
compatible clock signal.
T he CLK IN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. T he only exception is while the processor is in the Power-
down State. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual
for detailed information on
this powerdown feature.
If an external clock is used, it should be a T T L-compatible sig-
nal running at half the instruction rate. T he signal is connected
to the processor’s CLK IN input. When an external clock is
used, the X T AL input
must
be left unconnected.
T he ADSP-217x uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally, in-
structions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLK OUT signal when enabled.
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