參數(shù)資料
型號(hào)： ADSP-2173
廠商： Analog Devices, Inc.
英文描述： DSP Microcomputer(DSP 微計(jì)算機(jī))
中文描述： 微機(jī)的DSP（數(shù)字信號(hào)處理器微計(jì)算機(jī)）
文件頁(yè)數(shù)： 42/52頁(yè)
文件大小： 685K
代理商： ADSP-2173
REV. A
–42–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 1)
T iming Requirement:
t
HALP
t
HASU
t
HAH
t
HALS
t
HSU
t
HDSU
t
HWDH
t
HH
t
HRWP
ALE Pulse Width
HAD15–0 Address Setup before ALE Low
HAD15–0 Address Hold after ALE Low
Start of Write or Read after ALE Low
1
HRW Setup before Start of Write or Read
1
HAD15–0 Data Setup before End of Write
2
HAD15–0 Data Hold after End of Write
2
HRW Hold after End of Write or Read
2
Read or Write Pulse Width
3
15
5
2
15
8
8
3
3
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristic:
t
HSHK
t
HK H
t
HDE
t
HDD
t
HRDH
t
HRDD
HACK
Low after Start of Write or Read
1
HACK
Hold after End of Write or Read
2
HAD15–0 Data Enabled after Start of Read
1
HAD15–0 Data Valid after Start of Read
1
HAD15–0 Data Hold after End of Read
2
HAD15–0 Data Disabled after End of Read
2
0
0
0
20
20
ns
ns
ns
ns
ns
ns
23
0
15
NOT ES
1
Start of Write or Read =
HDS
Low and
HSEL
Low.
2
End of Write or Read =
HDS
High and
HSEL
High.
3
Read or Write Pulse Width =
HDS
Low and
HSEL
Low.
ADDRESS
t
HDSU
DATA
HACK
HRW
HSEL
HD15–0
t
HRWP
t
HSHK
ALE
t
HALP
t
HALS
t
HKH
t
HAH
t
HASU
t
HWDH
HDS
t
HH
t
HSU
ADDRESS
DATA
HACK
HRW
HSEL
HD15–0
t
HRWP
t
HSHK
ALE
t
HALP
t
HALS
t
HKH
t
HAH
t
HASU
t
HRDH
HDS
t
HH
t
HSU
t
HDE
t
HDD
t
HRDD
Figure 33. Host Interface Port (HMD1 = 1, HMD0 = 1)
Host Write Cycle
Host Read Cycle
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