參數(shù)資料
型號: ADSP-21368BBPZ-2A
廠商: Analog Devices Inc
文件頁數(shù): 26/64頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 333MHZ 256-BGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI
時鐘速率: 333MHz
非易失內(nèi)存: ROM(768 kB)
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 256-BGA(27x27)
包裝: 托盤
Rev. F
|
Page 32 of 64
|
October 2013
Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
masters, accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
strobe timing parameters only applies to asynchronous access
mode.
Table 25. Memory Write
Parameter
Min
Max
Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects1, 2
t
SDCLK – 9.7 + W
ns
t
DSAK
ACK Delay from WR Low 1, 3
W – 4.9
ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
t
SDCLK –3.1 + W
ns
t
DAWL
Address, Selects to WR Low
t
SDCLK –2.7
ns
t
WW
WR Pulse Width
W – 1.3
ns
t
DDWH
Data Setup Before WR High
t
SDCLK –3.0 + W
ns
t
DWHA
Address Hold After WR Deasserted
H + 0.15
ns
t
DWHD
Data Hold After WR Deasserted
H + 0.02
ns
t
WWR
WR High to WR, RD Low
t
SDCLK –1.5 + H
ns
t
DDWR
Data Disable Before RD Low
2t
SDCLK – 4.11
ns
t
WDE
Data Enabled to WR Low
t
SDCLK – 3.5
ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK.
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK.
1 ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.
2 The falling edge of MSx is referenced.
3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
Figure 20. Memory Write
ACK
DATA
tDAWH
tDWHA
tWWR
tDATRWH
tDWHD
tWW
tDDWR
tDDWH
tDAWL
tWDE
tDSAK
tDAAK
RD
WR
ADDR
MSx
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