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參數(shù)資料
| 型號： | ADS62C17IRGCR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 47/68頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 11BIT SRL/PAR 200M 64VQFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1.1W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-VQFN 裸露焊盤（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，單極 |
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CLKP
CLKM
VCM
0.1 F
m
0.1 F
m
CMOSclockinput
GAIN PROGRAMMABILITY
OFFSET CORRECTION
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
Figure 55. Single-Ended Clock Driving Circuit
ADS62C17 includes gain settings that can be used to get improved SFDR performance (compared to 0dB gain).
The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input full-scale
range scales proportionally, as shown in Table 11.
The SFDR improvement is achieved at the expense of SNR; for each 1dB gain step, the SNR degrades about
1dB. The SNR degradation is less at high input frequencies. As a result, the gain is very useful at high input
frequencies as the SFDR improvement is significant with marginal degradation in SNR.
So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB.
Table 11. Full-Scale Range Across Gains
Gain, dB
Full-Scale, Vpp
0
2V
1
1.78
2
1.59
3
1.42
4
1.26
5
1.12
6
1.00
ADS62C17 has an internal offset correction algorithm that estimates and corrects dc offset up to +/-10mV. The
correction can be enabled using the serial register bit <OFFSET CORRECTION ENABLE>. Once enabled, the
algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the
correction loop is a function of the sampling clock frequency. The time constant can be controlled using register
bits <OFFSET CORR TIME CONSTANT> as described in Table 12.
After the offset is estimated, the correction can be frozen by setting <OFFSET CORRECTION ENABLE> = 0.
Once frozen, the last estimated value is used for offset correction every clock cycle. The correction does not
affect the phase of the signal. Note that offset correction is disabled by default after reset.
Figure 56 shows the time response of the offset correction algorithm, after it is enabled.
Copyright 2009, Texas Instruments Incorporated
51
Product Folder Link(s): ADS62C17
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