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參數(shù)資料
| 型號： | ADS62C17IRGCR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 38/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 11BIT SRL/PAR 200M 64VQFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1.1W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-VQFN 裸露焊盤（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，單極 |
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APPLICATION INFORMATION
THEORY OF OPERATION
ANALOG INPUT
INP
INM
10 W
RCRFilter
Sampling
capacitor
Sampling
switch
Sampling
switch
Ron
15 W
Ron
100 W
3pF
Lpkg~ 2 nH
Sampling
capacitor
Ron
10 W
Lpkg~ 2 nH
C
~1pF
bond
R
200 W
R
200 W
C
~1pF
bond
3pF
100 W
C2
0.5pF
C1
0.25pF
C2
0.5pF
15 W
C
2pF
samp
C
2pF
samp
10 W
Drive Circuit Requirements
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
ADS62C17 is a low power 11-bit pipeline A/D converters with maximum sampling rate up to 200 MSPS.
At every falling edge of the input clock, the analog input signal of each channel is sampled simultaneously. The
sampled signal in each channel is converted by a pipeline of low resolution stages. In each stage, the sampled
and held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between the
stage input and its quantized equivalent is gained and propagates to the next stage. At every clock, each
succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are
combined in a digital correction logic block and processed digitally to create the final 11 bit code, after a data
latency of 22 clock cycles.
The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or
binary 2s complement format.
The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with
2V pp amplitude) and about 800MHz (with 1V pp amplitude).
The analog input consists of a switched-capacitor based differential sample and hold architecture.
This differential topology results in very good AC performance even for high input frequencies at high sampling
rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on
VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between
VCM + 0.5V and VCM – 0.5V, resulting in a 2Vpp differential input swing.
Figure 43. Analog Input Circuit
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A 5
to 15 resistor in series with each input pin is
recommended to damp out ringing caused by package parasitic.
SFDR performance can be limited due to several reasons - the effect of sampling glitches (described below),
non-linearity of the sampling circuit & non-linearity of the quantizer that follows the sampling circuit.
Depending on the input frequency, sample rate & input amplitude, one of these plays a dominant part in limiting
performance.
At very high input frequencies (> about 300 MHz), SFDR is determined largely by the device’s sampling circuit
non-linearity. At low input amplitudes, the quantizer non-linearity usually limits performance.
Copyright 2009, Texas Instruments Incorporated
43
Product Folder Link(s): ADS62C17
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