參數(shù)資料
型號(hào): ADS62C17IRGCR
廠商: Texas Instruments
文件頁數(shù): 46/68頁
文件大小: 0K
描述: IC ADC 11BIT SRL/PAR 200M 64VQFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 11
采樣率(每秒): 200M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1.1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
CLKP
VCM
2 pF
Lpkg
~ 2 nH
Lpkg
~2 nH
CLKM
Clockbuffer
Ceq
Ceq~ 1 to 3 pF, equivalentinputcapacitanceofclockbuffer
C
~1pF
bond
R
~100 W
20 W
C
~1pF
bond
R
~100 W
5kW
CLKP
CLKM
0.1 F
m
0.1 F
m
Differentialsine-wave
orPECL orLVDSclockinput
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
Figure 53. Internal Clock Buffer
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
Figure 54. Differential Clock Driving Circuit
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM tied to 1.5V common-mode voltage.
As shown in Figure 55, CLKM can be tied to VCM pin.
50
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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