參數(shù)資料
型號(hào)： ADS62C17IRGCR
廠商： Texas Instruments
文件頁(yè)數(shù)： 44/68頁(yè)
文件大?。?/td> 0K
描述： IC ADC 11BIT SRL/PAR 200M 64VQFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 11
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1.1W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，單極
A7
A6
A1
A0
D7
D6
D1
D0
Register address = 0x59
Register data = 0x01
SDATA
SCLK
SEN
CLKM
CLKP
N-26
Output
Data
clock
cycle 1
clock
cycle 9
clock
cycle 10
N-25
Serial register write to enable SNRBoost
10 clock cycles after the 16
th SCLK
falling edge, the device starts
giving out valid SNRBoost data
Valid SNRBoost
data starts
N-1
N
N+1
Analog
Input
Signal
CLOCK INPUT
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
Table 10. Positioning the Corner Frequency (Some Examples)
SNRBoost Coefficient1,
Normalized Corner
SNRBoost Coefficient1,
Normalized Corner
Center Frequency
Frequency1
Frequency2
<SNRBoost Coeff1>
<SNRBoost Coeff2>
(f/fs)
0
0.250
0
0.250
Fs × 0.25
F
0.230
1
0.270
Fs × 0.25
6
0.385
2
0.290
Fs × 0.3375
D
0.189
B
0.143
Fs × 0.166
9
0.080
7
0.420
Fs × 0.25
Figure 52. SNRBoost Active Delay
SNRBoost does not introduce any group delay in the input signal path. The ADC latency increases by four clock
cycle (to 26 clock cycles). When it is enabled using the serial interface, the mode becomes fully active 10 input
clock cycles after the 16th SCLK falling edge. When it is disabled, normal data (without SNRBoost) resumes after
6 clock cycle.
ADS62C17 clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM
using internal 5-k
resistors as shown in Figure 53. This allows using transformer-coupled drive circuits for sine
wave clock or ac-coupling for LVPECL, LVDS clock sources (Figure 54 and Figure 55).
Copyright 2009, Texas Instruments Incorporated
49
Product Folder Link(s): ADS62C17
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