參數(shù)資料
型號: ADS1259BIPW
廠商: Texas Instruments
文件頁數(shù): 31/48頁
文件大小: 0K
描述: IC ADC 24BIT 14KSPS LN 20TSSOP
產(chǎn)品培訓(xùn)模塊: Industrial Automation Overview
標(biāo)準(zhǔn)包裝: 70
位數(shù): 24
采樣率(每秒): 14k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
其它名稱: 296-27183-5
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
CONFIG2: CONFIGURATION REGISTER 2 (Address = 2h)
7
6
5
4
3
2
1
0
DRDY
EXTCLK
SYNCOUT
PULSE
0
DR2
DR1
DR0
Reset value = XX000000b.
Bit 7
DRDY: Data ready (read-only)
This bit duplicates the state of the DRDY pin. Poll this bit to indicate that data are ready. When
DRDY is low, data are ready.
Bit 6
EXTCLK: Clock source (read-only)
0 = Device clock source is internal oscillator
1 = Device clock source is external clock
Note that the ADS1259 selects the clock source automatically.
Bit 5
SYNCOUT: SYNCOUT clock enable
0 = SYNCOUT disabled (default)
1 = SYNCOUT enabled
Note that if disabled, the output is driven low.
Bit 4
PULSE: Conversion Control mode select
0 = Gate Control mode (default)
1 = Pulse Control mode
Bit 3
Reserved
Always write '0'
Bits 2-0
DR[2:0] Data rate setting
000 = 10SPS (default)
001 = 16.6SPS
010 = 50SPS
011 = 60SPS
100 = 400SPS
101 = 1200SPS
110 = 3600SPS
111 = 14400SPS
NOTE: fCLK = 7.3728MHz
Copyright
2009–2011, Texas Instruments Incorporated
37
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