參數(shù)資料
型號(hào)： ADE7753ARSRL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Active and Apparent Energy Metering IC with di/dt sensor interface
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： MO-150AE, SSOP-20
文件頁(yè)數(shù)： 14/38頁(yè)
文件大小： 449K
代理商： ADE7753ARSRL
ADE7753
–14–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
T E MPE RAT URE ME ASURE ME NT
ADE7753 also includes an on-chip temperature sensor. A
temperature measurement can be made by setting bit 5 in the
Mode register. When bit 5 is set logic high in the Mode
register, the ADE7753 will initiate a temperature measure-
ment on the next zero crossing. When the zero crossing on
Channel 2 is detected the voltage output from the tempera-
ture sensing circuit is connected to ADC1 (Channel 1) for
digitizing. T he resultant code is processed and placed in the
T emperature register (T EMP[7:0]) approximately 26μs later
(24 C L K IN cycles). If enabled in the Interrupt Enable
register (bit 5), the
IRQ
output will go active low when the
temperature conversion is finished. Please note that tempera-
ture conversion will introduce a small amount of noise in the
energy calculation. If temperature conversion is performed
frequently (e.g. multiple times per second), a noticeable
error will accumulate in the resulting energy calculation over
time.
T he contents of the T emperature register are signed (2's
complement) with a resolution of approximately 1 LSB/°C.
T he temperature register will produce a code of 00h when the
ambient temperature is approximately 70°C. T he tempera-
ture measurement is uncalibrated in the ADE7753 and has an
offset tolerance that could be as high as ±20°C.
ADE 7753 ANALOG T O DIGIT AL CONVE RSION
T he analog-to-digital conversion in the ADE7753 is carried
out using two second order sigma-delta ADCs. For simplic-
ity reason, the block diagram in Figure 17 shows a first order
sigma-delta ADC. T he converter is made up of two parts: the
sigma-delta modulator and the digital low pass filter.
V
REF
+
-
....10100101......
Digital Low Pass Filter
Σ
e
MCLK/4
INTEGRATOR
1-Bit DAC
LATCHED
COMPARATOR
+
-
R
C
Analog Low Pass Filter
24
Figure 17– First Order Sigma-Delta (
Σ
) ADC
A sigma-delta modulator converts the input signal into a
continuous serial stream of 1's and 0's at a rate determined by
the sampling clock. In the ADE7753 the sampling clock is
equal to CLK IN/4. T he 1-bit DAC in the feedback loop is
driven by the serial data stream. T he DAC output is sub-
tracted from the input signal. If the loop gain is high enough
the average value of the DAC output (and therefore the bit
stream) will approach that of the input signal level. For any
given input value in a single sampling interval, the data from
the 1-bit ADC is virtually meaningless. Only when a large
number of samples are averaged will a meaningful result be
obtained. T his averaging is carried out in the second part of
the ADC, the digital low pass filter. By averaging a large
number of bits from the modulator the low pass filter can
produce 24-bit data words which are proportional to the input
signal level.
T he sigma-delta converter uses two techniques to achieve
high resolution from what is essentially a 1-bit conversion
technique. T he first is over-sampling. By over sampling we
mean that the signal is sampled at a rate (frequency) which is
many times higher than the bandwidth of interest. F or
example the sampling rate in the ADE7753 is C L K IN/4
(894kHz) and the band of interest is 40Hz to 2kHz. Over-
sampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the
noise spread more thinly over a wider bandwidth, the
quantization noise in the band of interest is lowered—see
Figure 18. However, oversampling alone is not an efficient
enough method to improve the signal to noise ratio (SNR) in
the band of interest. For example, an oversampling ratio of
4 is required just to increase the SNR by only 6dB (1-Bit). T o
keep the oversampling ratio at a reasonable level, it is
possible to shape the quantization noise so that the majority
of the noise lies at the higher frequencies. T his is what
happens in the sigma-delta modulator, the noise is shaped by
the integrator which has a high pass type response for the
quantization noise. T he result is that most of the noise is at
the higher frequencies where it can be removed by the digital
low pass filter. T his noise shaping is also shown in Figure 18.
Frequency (Hz)
0
447kHz
894kHz
2kHz
Sampling
Frequency
Shaped
Noise
Antialias filter (RC)
Digital filter
Noise
Signal
Frequency (Hz)
0
447kHz
894kHz
2kHz
Noise
Signal
High resolution
output from Digital
LPF
Figure 18– Noise reduction due to Oversampling & Noise
shaping in the analog modulator
scribed, when the
IRQ
output goes low the MCU ISR must
read the Interrupt Status register in order to determine the
source of the interrupt. When reading the Status register
contents, the
IRQ
output is set high on the last falling edge
of SC L K of the first byte transfer (read Interrupt Status
register command). T he
IRQ
output is held high until the last
bit of the next 15-bit transfer is shifted out (Interrupt Status
register contents)— see Figure 16. If an interrupt is pending
at this time, the
IRQ
output will go low again. If no interrupt
is pending the
IRQ
output will stay high.
Antialias Filter
Figure 17 also shows an analog low pass filter (RC) on the
input to the modulator. T his filter is present to prevent
aliasing. Aliasing is an artifact of all sampled systems.
Basically it means that frequency components in the input
signal to the ADC which are higher than half the sampling
rate of the ADC will appear in the sampled signal at a
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