參數(shù)資料
型號： ADAV803ASTZ-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù)： 43/56頁
文件大?。?/td> 906K
代理商： ADAV803ASTZ-REEL
ADAV803
Table 47. Receiver Channel S
ADDRESS
= 0100
RCSB7–0
Rev. 0 | Page 43 of 56
tatus Buffer
SB0
B7–RC
7, 6, 5, 4, 3, 2, 1, 0
000 to 01
10111
The 24-byte receiver channel status buffer. The PRO b
only if the channel status is not autob
RCS
(0x20 to
0x37)
d at ad
ceiver an
tion 0
mitter.
This bu
d
betwee
it is store
n the re
dress loca
d trans
x20, Bit 0.
ffer is rea
uffered
Table 48. T
ADDRESS
TCSB7–0
ter Ch
TCS
7, 6, 5, 4, 3, 2, 1, 0
to 10
= 0111000
The 24-byte transmi
disa
tus Bu
B0
ransmit
annel Sta
B7–TCS
ffer
38 to
01111 (0x
0x4F)
tter chann
uffering b
el stat
etwee
The PR
iver and transmitter is
n the rece
tored a
location 0x38, Bit 0. This buffer is
t address
enabled.
autob
us buffer.
O bit is s
bled when
Table 49. Receiver User Bit Buffer Indire
ADDRESS = 1010000 (0x50)
RxUBADDR07–00
ess Regi
RxUBADDR07–RxUBADDR00
7, 6, 5, 4, 3, 2, 1, 0
ct Addr
ster
ng to th
ss loca
he rece
r bit bu
Indirect address pointi
e addre
tion in t
iver use
ffer.
Table 50. Receiver Us
ADDRESS = 1010001 (0x51)
RxUBDATA07–00
07–RxUBDATA00
er Bit Buffer Data Register
RxUBDATA
7, 6, 5, 4, 3, 2, 1, 0
egister reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR07–
ering of the user bits is enabled; otherwise, it is a read-only buffer.
00. This buffer can be written to when autobuff
A read from this r
Table 51. Transmitte
ADDRESS = 1010010 (0x52)
TxUBADDR07–00
Indirect Address Register
BADDR00
r User Bit Buffer
TxUBADDR07–TxU
7, 6, 5, 4, 3, 2, 1, 0
ress pointing to the address location in the transmitter user bit buffer.
Indirect add
Table 52. Transmitter User Bit Buffer
ADDRESS = 1010011 (0x53)
TxUBDATA07–00
DATA00
Data Register
07–TxUB
TxUBDATA
7, 6, 5, 4, 3, 2, 1, 0
A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR07–00.
When user bit autobuffering is enabled, this buffer is disabled.
Table 53. Q Subcode CRCError Status Register (Read-Only)
RES
7
ADDRESS = 1010100 (0x54)
QCRCERROR
This bit is set, if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This
bit is cleared once the register is read.
QSUB
This bit is set, if a Q subcode has been read into the Q subcode buffer (see Table 54).
RES
6
RES
5
RES
4
RES
3
RES
2
QCRCERROR
1
QSUB
0
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