參數(shù)資料
型號(hào)： ADAV803ASTZ-REEL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 15/56頁(yè)
文件大小： 906K
代理商： ADAV803ASTZ-REEL
ADAV803
FUNCTIONAL DESCRIP
ADC SECTION
The ADAV803’s ADC section is implemented using a second-
order multibit (5 bits)
Σ
-
modulator. The modulator is
sampled at either half of the ADC MCLK rate (modulator clo
= 128 × f
S
) or one-quarter of the ADC MCLK rate (modulator
clock = 64 × f
S
). The digital decimator consists of a Sinc^5 filter
followed by a cascade of three half-band FIR filters. The Sin
decimates by a factor of 16 at 48 kHz
96 kHz. Each of the half-band filters decimates by a factor of 2.
Figure 23 shows the details of the ADC section. The ADC can
be clocked by a number of different clock sources to control t
sample rate. MCLK selection for the ADC is set by Internal
Clocking Control Register 1 (Address 0x76). The ADC provide
an output word of up to 24 bits of resolution in twos comple-
ment format. The output word can be routed to ei
output ports, the sample rate converter, or the SPDIF digital
transmitter.
D
S
)
Rev. 0 | Page 15 of 56
TION
ck
c
and by a factor of 8 at
he
s
ther the
P
P
M
X
REG 0x76
BITS 4–2
REG 0x6F
BITS 1–0
0
D
S
)
ADC MCLK
DIVIDER
ADC
MCLK
ADC
Figure 23. Clock Path Control on the ADC
Programmable Gain Amplifier (PGA)
The input of the record channel features a PGA that converts
the single-ended signal to a differential signal, which is applied
to the analog Σ-Δ modulator of the ADC. The PGA can be
programmed to amplify a signal by up to 24 dB in 0.5 dB
increments. Figure 24 shows the structure of the PGA circuit.
4k
TO 64k
125
CAPxN
EXTERNAL
CAPACITOR
(1nF NPO)
VREF
TO
MODULATOR
EXTERNAL
CAPACITOR
(1nF NPO)
CAPxP
EXTERNAL
CAPACITOR
(1nF NPO)
8k
8k
0
4k
125
Figure 24. PGA Block Diagram
Analog Σ- Modulator
The ADC features a second-order, multibit, Σ-Δ modulator. The
input features two integrators in cascade followed by a flash
converter. This multibit output is directed to a scrambler,
followed by a DAC for loop feedback. The flash ADC output is
also converted from thermometer coding to binary coding for
input as a 5-bit word to the decimator. F
ADC block diagram.
igure 25 shows the
The ADC also features independent digital volume control for
the left and right channels. The volume control consists of
256 linear steps, with each step reducing the digital output
codes by 0.39%. Each channel also has a peak detector that
records the peak level of the input signal. The peak detector
register is cleared by reading it.
ADC MODCLK
MULTI-BIT
Σ
–
MODULATOR
DECIMATOR
HPF
PEAK
DETECT
VOLUME
CONTROL
0
SINC^5
HALF-BAND
FILTER
ADC MCLK/2
(TYP 6.144MHz)
384kHz
768kHz
192k
384k
SINC
COMPENSATION
Hz
Hz
HALF-BAND
FILTER
96kHz
192kHz
48kHz
96kHz
Diagram
Figure 25
. ADC Block
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