參數(shù)資料
型號： ADAV803ASTZ-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù)： 28/56頁
文件大?。?/td> 906K
代理商： ADAV803ASTZ-REEL
ADAV803
Rev. 0 | Page 28 of 56
0
REG 0x76
BITS 4–2
DIR PLL(512 ×
f
S
)
DIR PLL(256 ×
f
S
)
PLLINT1
PLLINT2
MCLKI
XIN
ICLK1
ICLK2
PLL CLOCK
REG 0x06
BITS 4–3
MCLK
ADC
OUTPUT
PORT
OLRCLK
OBC
OSDATA
LK
REG 0x76
BITS 7–5
DIR PLL(512 ×
f
S
)
DIR PLL(256 ×
f
S
)
PLLINT1
PLLINT2
MCLKI
XIN
ICLK1
ICLK2
PLL CLOCK
REG 0x04
BITS 4-3
MCLK
DAC
INPUT
PORT
ILRCLK
IBC
ISDATA
LK
REG 0x77
BITS 4–3
REG 0x00
BITS 3–2
DIVIDER
BITS 1–0
ICLK1
REG 0x00
BITS 4–5
REG 0x76
BITS 1–0
MCLKI
XIN
PLLINT1
PLLINT2
REG 0x00
ICLK2
DIR PLL(512 ×
f
S
)
DIR PLL(256 ×
f
S
)
REG 0x00
BITS 1-0
MCLKI
XIN
PLLINT1
PLLINT2
DIVIDER
DIVIDER
SRC
MCLK
Figure 50. SPORT Clocking Scheme
Care should be taken to ensure that the clock rate is appropriate
for whatever block is connected to the serial port. For example,
if the ADC is running from the MCLKI input at 256 × f
S
, then
the master clock for the SPORT should also run from the
MCLKI input to ensure that the ADC and serial port are
synchronized.
The SPORTs can be set to transmit or receive data in I
2
S, left-
justified or right-justified formats with different word lengths
by programming the appropriate bits in the playback register,
auxiliary input port register, record register, and auxiliary
output port-control register. Figure 51 is a timing diagram of
the serial data port formats.
Clocking Scheme
The ADAV803 provides a f
chip clocking sources. The on-c
intended to offer complete system clocking requirements for
use with available MPEG encoders, decoders, or a combination
of codecs. The oscillator function is designed for generation of a
27 MHz video clock from a 27 MHz crystal connected between
the XIN and XOUT pins. Capacitors must also be connected
between these pins and DGND, as shown in Figure 35. The
capacitor values should be specified by the crystal manufacturer.
A square wave version of the crystal clock is output on the
MCLKO pin. If the system has a 27 MHz clock available, this
clock can be connected directly to the XIN pin.
f on-chip and off-
tor with dual PLLs is
hip oscilla
lexible choice o
0
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LSB
LSB
LSB
LSB
LSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
MSB
MSB
MSB
MSB
RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL
I
2
S MODE — 16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL
Figure 51. Serial Data Modes
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