參數(shù)資料
型號： ADAV803ASTZ-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù)： 41/56頁
文件大?。?/td> 906K
代理商： ADAV803ASTZ-REEL
ADAV803
Table 42. Sample Rate Converter Error Ma
Rev. 0 | Page 41 of 56
sk Register
RES
5
ADDRESS = 0011011 (0x1B)
OVRL Mask
OVRR Mask
MUTE_IND M
RES
6
RES
4
RES
3
OVRL Mask
2
sk
E_
RES
7
OVRR Ma
1
MUT
0
IND MASK
Masks the OVRL from generating an interrupt.
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
Masks the OVRR from generating an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
Masks the MUTE_IND from generating an
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.
ASK
interrupt.
Table 43. Interrupt St
ADDRESS = 0011100 (0x1C)
SRCError
TxCSINT
4
RxCSDIFF
3
RxUBINT
2
RxCSBINT
1
RxERROR
0
atus Register
SRCError
7
TxCSTINT
6
TxUBINT
5
This bit is set, if one of the sample rate converter interrupts is asserted, and the host should immediately read the
gh until the interrupt status register is read.
sample rate converter error register. This bit remains hi
This bit is set, if a write to the transmitter channel status buffer was made while transmitter channel status bits were
fer to the SPDIF transmit buffer.
his bit remains high until the interrupt status register is read.
it buffer has transmitted its block of channel status. This bit remains
This bit is set, if the transmitter channel status b
high until the interrupt status register is read.
This bit is set, if the receiver Channel Status A block is different from the re
TxCSTINT
ceiver Channel Status B clock. This bit
remains high until read, but does not generate an interrupt.
eiver user bit buffer has a new block or message. This bit remains high until the interrupt
This bit is set, if the rec
status register is read.
This b
a new
hannel sta
d when RxBC NF3 =
Rx
Th
hi
This bit
receiver error register. This bit rema
RxCSBIN
it is set, if
BCONF3 = 1.
is set, if one of the AES3/SPDIF receiver interrupts is asserted, and the host should immediately read the
ins high until the interrupt status register is read.
block of c
is bit remains
tus is rea
O
0, or if the
when
gh until the interrupt status register is read.
being copied from the transmitter CS buf
This bit is set, if the SPDIF transmit buffer is empty. T
TxUBINT
TxCSINT
RxCSDIFF
RxUBINT
T
channel status ha changed
RxERROR
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