參數(shù)資料
型號(hào): ADAU1446YSTZ-3A
廠商: Analog Devices Inc
文件頁(yè)數(shù): 10/92頁(yè)
文件大?。?/td> 0K
描述: IC SIGMADSP 175MHZ 100LQFP
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
類型: 音頻處理器
應(yīng)用: 車載音頻
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(16x16)
包裝: 托盤
ADAU1445/ADAU1446
Rev. A | Page 18 of 92
INITIALIZATION
Power-Up Sequence
The ADAU1445/ADAU1446 have a built-in initialization period,
which allows sufficient time for the PLL to lock and the registers
to initialize their values. On a positive edge of RESET, the PLL
settings are immediately set by the PLL0, PLL1, and PLL2 pins,
and the master clock signal is blocked from the chip subsystems.
The initialization time lasts 10 ms, which is measured from the
rising edge of RESET. New values should not be written via the
control port until the initialization is complete.
Table 6 shows some typical times to boot the ADAU1445/
ADAU1446 into the operational state necessary for an application,
assuming that a 400 kHz I2C clock or a 5 MHz SPI clock is used
and a full program, parameter set, and all registers (9 kB) are
loaded. In reality, most applications use less than this full amount,
and unused program and parameter RAM need not be initialized;
therefore, the total boot time may be shorter.
Recommended Program/Parameter Loading Procedure
When writing large amounts of data to the program or parameter
RAM in direct write mode, such as when downloading the initial
contents of the RAMs from an external memory, the processor core
should be disabled to prevent unpleasant noises from appearing
at the audio output. When small amounts of data are transmitted
during real-time operation of the DSP, such as when updating
individual parameters, the software safeload mechanism can be
used. More information is available in the Software Safeload section.
Power-Reduction Modes
Sections of the ADAU1445/ADAU1446 chips can be turned on
and off as needed to reduce power consumption. These include
the ASRCs, S/PDIF receiver and transmitter, auxiliary ADCs,
and DSP core. More information is available in the Master
System Initialization Sequence
Before the IC can process audio in the DSP, the following initial-
ization sequence must be completed. (Step 5 through Step 11
can be performed in any order, as needed.)
1.
Power on the IC and bring it out of reset. The order of the
power supplies (DVDD, IOVDD, and AVDD) does not matter.
2.
Wait at least 10 ms for the initialization to complete.
3.
Enable the master clocks of all modules to be used (see the
4.
Deassert the core run bit (see the DSP Core Modes and
Settings section).
5.
Set the serial input modes (see the Serial Input Port Modes
6.
Set the serial output modes (see the Serial Output Port
7.
Set the routing matrix modes (see details of Address 0xE080
to Address 0xE09B in the Flexible Audio Routing Matrix
Modes section).
8.
Set the DSP core rate select registers (see the DSP Core
9.
Write the parameter RAM (Address 0x0000 to Address
0x0FFF).
10. Write the program RAM (Address 0x2000 to Address
0x2FFF).
11. Write all other necessary control registers, such as ASRCs
and S/PDIF (Address 0xE221 to Address 0xE24C).
12. Assert the core run bit (see the DSP Core Modes and
Settings section).
Table 6. Power-Up Time
PLL Lock Time (ms)
Approximate Boot Time; Loading Maximum Program/Parameter/Registers (ms)
Total (ms)
I2C (@ 400 kHz SCL)
SPI (@ 5 MHz CCLK)
SPI (@ 25 MHz CCLK)
10
25
2
0.4
10.4 to 35
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ADAU1446YSTZ-3A-RL 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP(10x10) 包裝:Digi-Reel® 其它名稱:497-11050-6
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ADAU1451WBCPZ 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包裝:托盤 零件狀態(tài):有效 類型:Sigma 接口:I2C,SPI 時(shí)鐘速率:294.912MHz 非易失性存儲(chǔ)器:- 片載 RAM:96kB 電壓 - I/O:3.3V 電壓 - 內(nèi)核:1.20V 工作溫度:-40°C ~ 105°C(TA) 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤,CSP 供應(yīng)商器件封裝:72-LFCSP-VQ(10x10) 標(biāo)準(zhǔn)包裝:1
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