參數(shù)資料
型號(hào)： ADAU1445YSVZ-3A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/92頁(yè)
文件大?。?/td> 0K
描述： IC SIGMADSP 175MHZ 100TQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車載音頻
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤(pán)
ADAU1445/ADAU1446
Rev. A | Page 38 of 92
Bit Position
Description
Default
[7:6]
Word length
00
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = flexible TDM mode3
[5:3]
MSB position
000
000 = I2S (delayed by 1)
001 = left justified (delayed by 0)
010 = delayed by 8
011 = delayed by 12
100 = delayed by 16
[2:0]
TDM type
000
000 = TDM2 (stereo)
001 = TDM4
010 = TDM8 or flexible TDM mode3
011 = TDM16
100 = packed TDM4
1 Bit 15 and Bits[13:10] must be used in conjunction to set the port as a master or slave.
2 The default depends on the address: 0xE000 = 0001, 0xE001 = 0010, 0xE002 = 0011, 0xE003 = 0100, 0xE004 = 0101, 0xE005 = 0110, 0xE006 = 0111, 0xE007 = 1000, and
0xE008 = 1001.
3 To activate flexible TDM mode, both Bits[7:6] and Bits[2:0] must be set.
Clock Output Enable Bit (Bit 15)
This bit controls the serial port’s respective bit clock as well as
the left and right clocks. When this bit is set to 1, the clock pins
are set to output. When this bit is set to 0, the clock pins are not
output clocks. In Register 0xE000 to Register 0xE008, Bit 15 and
Bits[13:10] must be used in conjunction to set the port as a master
or slave. Clock domains are assigned to input or output serial
ports with the clock pad multiplexer register (Address 0xE240).
For more information, see the Clock Pad Multiplexer section.
Frame Sync Type Bit (Bit 14)
This bit sets the type of LRCLK signal that is used. When this
bit is set to 0, the clock signal is a square wave. When this bit is
set to 1, the signal is a narrow pulse.
Clock Domain Master/Slave Select Bits (Bits[13:10])
These bits determine whether the serial port outputs its clocks
as a master or slave to an available clock domain. If a serial port
is set to be a master, the clock output enable bit (Bit 15) must be
set to 1. If a serial port is set as a slave, the clock output enable
bit must be set to 0. In both cases, the corresponding clock pad
multiplexer must be set to the serial input domain, if assignable.
For more information, see the Clock Pad Multiplexer section. Note
that an arbitrary number of serial ports can be slaves to a single
clock domain, but a single serial port can only be a master to one
clock domain. The values for fS,NORMAL, fS,DUAL, and fS,QUAD are 48 kHz,
96 kHz, and 192 kHz, respectively, for a 172.032 MHz core clock
signal.
Serial Input BCLK Polarity Bit (Bit 9)
The polarity of BCLKx determines whether LRCLKx and
SDATA_INx change on a rising (+) or falling () edge of the
BCLKx signal. Standard I2S signals use negative BCLK polarity.
Serial Input LRCLK Polarity Bit (Bit 8)
The polarity of LRCLKx determines whether the left stereo channel
is initiated on a rising (+) or falling () edge of the LRCLKx signal.
Standard I2S signals use negative LRCLK polarity.
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