- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10240 > ADAU1445YSVZ-3A (Analog Devices Inc)IC SIGMADSP 175MHZ 100TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADAU1445YSVZ-3A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/92頁 |
| 文件大小： | 0K |
| 描述： | IC SIGMADSP 175MHZ 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADAU1445/ADAU1446
Rev. A | Page 27 of 92
SPI Port
By default, the ADAU1445/ADAU1446 are in I2C mode, but
these parts can be put into SPI control mode by pulling CLATCH
low three times. Each low pulse should have a minimum duration
of 20 ns, and the delay between pulses should be at least 20 ns.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1445/ADAU1446
on the falling edge of CCLK and should be clocked into a receiving
device, such as a microcontroller, on the next CCLK falling edge
(rising edge is possible if tCOV timing is met). The CDATA signal
carries the serial input data, and the COUT signal is the serial
output data. The COUT signal remains three-stated until a read
operation is requested. This allows other SPI-compatible periph-
erals to share the same readback line. All SPI transactions have
SPI port timing diagram). All data written should be MSB first.
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1445/ADAU1446 devices to share a CLATCH
signal, yet still operate independently. When ADDR0 is low, the
chip address is 0000000; when ADDR0 is high, the address is
0000001. The LSB of the first byte determines whether the SPI
transaction is a read (Logic Level 1) or a write (Logic Level 0).
Users can communicate with both ICs with up to five latch signals
by using the USBi communication channel list in the hardware
configuration tab in SigmaStudio.
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory or register locations. The detailed data
format for continuous mode operation is shown in Figure 4.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 19. A sample timing
diagram of a single SPI read operation is shown in Figure 20.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and R/W bit, and subsequent bytes carry the data.
Table 13. Generic Control Word Sequence
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
Chip Address[6:0], R/W
Subaddress[15:8]
Subaddress[7:0]
Data
1 Continues to end of data.
BYTE 3
BYTE 2
BYTE 0
BYTE 1
CLATCH
CCLK
CDATA
07
69
6-
0
19
Figure 19. SPI Write Clocking (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 0
BYTE 1
HIGH-Z
DATA
HIGH-Z
0
76
96
-02
0
Figure 20. SPI Read Clocking (Single-Read Mode)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-232-IW-S | CONVERTER MOD DC/DC 15V 100W |
| AD1941YSTZ | IC DSP AUDIO 16CHAN 28BIT 48LQFP |
| VI-B6Y-MX | CONVERTER MOD DC/DC 3.3V 49.5W |
| ADAU1446YSTZ-3A | IC SIGMADSP 175MHZ 100LQFP |
| VI-232-CU-F4 | CONVERTER MOD DC/DC 15V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1445YSVZ-3A-RL | 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1446EBZ | 制造商:Analog Devices 功能描述:SIGMADSP? DIGITAL AUDIO PROCESSOR WITH FLEXIBLE AUDIO - Bulk |
| ADAU1446YSTZ-3A | 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1446YSTZ-3A-RL | 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1450WBCPZ | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包裝:托盤 零件狀態(tài):有效 類型:Sigma 接口:I2C，SPI 時(shí)鐘速率:147.456MHz 非易失性存儲(chǔ)器:- 片載 RAM:64KB 電壓 - I/O:3.3V 電壓 - 內(nèi)核:1.20V 工作溫度:-40°C ~ 105°C（TA） 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP-VQ（10x10） 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。