參數(shù)資料
型號(hào)： AD9984APCBZ
廠商： Analog Devices, Inc.
英文描述： High Performance 10-Bit Display Interface
中文描述： 高性能10位顯示接口
文件頁(yè)數(shù)： 36/44頁(yè)
文件大小： 490K
代理商： AD9984APCBZ
AD9984A
Table 51. Output Mode Bits
Value
Result
100
4:4:4 RGB mode.
101
4:2:2 YCbCr mode.
110
4:4:4 DDR mode.
0x1F—Bit[4] Primary Output Enable
This bit places the primary output in active or high impedance
mode. The power-up default setting is 1.
Rev. 0 | Page 36 of 44
Table 52. Primary Output Enable Bit
Value
Result
0
Primary output is in high impedance mode.
1
Primary output is enabled.
0x1F—Bit[3] Secondary Output Enable
This bit places the secondary output in active or high
impedance mode.
The secondary output is designated when using either 4:2:2 or
4:4:4 DDR. In these modes, the data on the blue output channel
is the secondary output while the output data on the red and
green channels are the primary output. Secondary output is
always a DDR YCbCr data mode. See the Output Formatter
section and Table 12. The power-up default setting is 0.
Table 53. Secondary Output Enable Bit
Value
Result
0
Secondary output is in high impedance mode.
1
Secondary output is enabled.
0x1F—Bits[2:1] Output Drive Strength
These two bits select the drive strength for all the high speed
digital outputs (except VSOUT, A0, and O/E FIELD). Higher
drive strength results in faster rise/fall times and, in general,
makes it easier to capture data. Lower drive strength results in
slower rise/fall times and helps to reduce EMI and digitally gen-
erated power supply noise. The power-up default setting is 10.
Table 54. Output Drive Strength Bits
Value
Result
00
Low output drive strength.
01
Medium output drive strength.
1x
High output drive strength.
0x1F—Bit[0] Output Clock Invert
This bit allows inversion of the output clock. The power-up
default setting is 0.
Table 55. Output Clock Invert Bit
Value
Result
0
Noninverted pixel clock.
1
Inverted pixel clock.
0x20—Bits[7:6] Output Clock Select
These bits selects the optional output clocks such as a fixed 40 MHz
internal clock, a 2× clock, a 90° phase-shifted clock, or the normal
pixel clock. The power-up default setting is 00.
Table 56. Output Clock Select Bits
Value
Result
00
Pixel clock.
01
90° phase-shifted pixel clock.
10
2× pixel clock.
11
0.5× pixel clock.
0x20—Bit[5] Output High Impedance
This bit puts all outputs (except SOGOUT) in a high impedance
state. The power-up default setting is 0.
Table 57. Output High Impedance Bit
Value
Result
0
Normal outputs.
1
All outputs (except SOGOUT) in high impedance mode.
0x20—Bit[4] SOGOUT High Impedance
This bit allows the SOGOUT pin to be placed in high
impedance mode. The power-up default setting is 0.
Table 58. SOGOUT High Impedance Bit
Value
Result
0
Normal drive.
1
SOGOUT pin is in high impedance mode.
0x20—Bit[3] Field Output Polarity
This bit sets the polarity of the field output bit. The power-up
default setting is 1.
Table 59. Field Output Polarity Bit
Value
Result
0
Active low = even field, active high = odd field.
1
Active low = odd field, active high = even field.
SYNC PROCESSING
0x20—Bit[2] PLL Sync Filter Enable
This bit selects which signal the PLL uses. It can select between
raw versions of HSYNCx/SOGINx and filtered versions of
Hsync/SOG. The filtering of the Hsync and SOG can eliminate
nearly all extraneous transitions that have traditionally caused
PLL disruption. The power-up default setting is 0.
Table 60. PLL Sync Filter Enable Bit
Value
Result
0
PLL uses raw HSYNCx or SOGINx.
1
PLL uses filtered Hsync or SOG.
0x20—Bit[1] Sync Processing Input Select
This bit selects whether the sync processor uses a raw sync or a
regenerated Hsync for the following functions: coast, Hsyncs
per Vsync count, field detection, and Vsync duration counts.
Using the regenerated Hsync is recommended.
Table 61. Sync Processing Input Select Bit
Value
Result
0
Sync processing uses raw HSYNCx or SOGINx.
1
Sync processing uses the internally regenerated
Hsync.
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