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參數(shù)資料
| 型號： | AD9984APCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | 高性能10位顯示接口 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大?。?/td> | 490K |
| 代理商： | AD9984APCBZ |
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AD9984A
0x19—Bits[7:0] Clamp Placement
An 8-bit register that sets the position of the internally generated
clamp. When clamp source select = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally at a position established by
this register and for a duration set by the clamp duration register
(Register 0x1A). Clamping is started at the clamp placement
count of pixel periods after the trailing edge of Hsync. The clamp
placement can be programmed to any value between 1 and 255.
A value of 0 is not supported.
The clamp should be placed during a time that the input signal
presents a stable black-level reference, usually the back porch
period between Hsync and the image. When clamp source = 1,
this register is ignored. Power-up default setting is 8.
0x1A—Bits[7:0] Clamp Duration
An 8-bit register that sets the duration of the internally generated
clamp. When the clamp source select is 0 (Register 0x18, Bit 4),
a clamp signal is generated internally at a position established
by the clamp placement register (Register 0x19) for a duration
set by this clamp duration register. Clamping begins a clamp
placement count (Register 0x19) of pixel periods after the trailing
edge of Hsync. The clamp duration can be programmed to any
value between 1 and 255. A value of 0 is not supported.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
Hsync signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen, and a slow
recovery from large changes in the average picture level (APL)
or brightness. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 20d.
0x1B—Bit[7] Clamp Polarity Override
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The power-up
default setting is 0.
Rev. 0 | Page 34 of 44
Table 37. Clamp Polarity Override Bit
Value
Result
0
Clamp polarity determined by chip.
1
Clamp polarity determined by user (Register 0x1B, Bit 6).
0x1B—Bit[6] Clamp Polarity
This bit indicates the polarity of the clamp signal only if Bit 7 of
Register 0x1B = 1. The power-up default setting is 1.
Table 38. Clamp Polarity Bit
Value
Result
0
Clamp polarity is negative.
1
Clamp polarity is positive.
0x1B—Bit[5] Auto-Offset Enable
This bit selects between auto-offset mode and manual offset
mode (auto-offset disabled). See the Automatic Offset section
for more information. The power-up default setting is 0.
Table 39. Auto-Offset Enable Bit
Value
Result
0
Auto-offset is disabled.
1
Auto-offset is enabled (manual offset mode).
0x1B—Bits[4:3] Auto-Offset Update Frequency
These bits control how often the auto-offset circuit is updated
(if enabled). Updating every 192 Hsyncs recommended. The
power-up default setting is 11.
Table 40. Auto-Offset Update Frequency Bits
Value
Result
00
Update offset every 3-clamp periods.
01
Update offset every 48-clamp periods.
10
Update offset every 192-clamp periods.
11
Update offset every 3 Vsync periods.
0x1B—Bits[2:0]
Must be written to 011 for proper operation.
0x1C—Bits[7:0] Test Register 0
Must be set to 0xFF for proper operation.
SOG CONTROL
0x1D—Bits[7:3] SOG Slicer Comparator Threshold
These register bits adjust the comparator threshold of the SOG
slicer in steps of 8 mV, with the minimum setting equaling
8 mV and the maximum setting equaling 256 mV. The power-
up default setting is 15d and corresponds to a threshold value of
128 mV.
0x1D—Bit[2] SOGOUT Polarity
This bit sets the polarity of the SOGOUT signal. The power-up
default setting is 0.
Table 41. SOGOUT Polarity Bit
Value
Result
0
SOGOUT polarity is negative.
1
SOGOUT polarity is positive.
0x1D—Bits[1:0] SOGOUT Select
These register bits control what is output on the SOGOUT pin.
Options are the raw SOGINx from the slicer (that is, the unproc-
essed SOG signal produced from the sync slicer), the raw HSYNCx,
the regenerated Hsync from the sync filter that can generate
missing syncs due to coasting or drop-out, or finally, the filtered
Hsync that excludes extraneous syncs that do not occur within
the sync filter window. The power-up default setting is 0.
Table 42. SOGOUT Select Bits
Value
Result
00
Raw SOGINx.
01
Raw HSYNCx.
10
Regenerated Hsync from sync filter.
11
Filtered Hsync from sync filter.
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