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參數(shù)資料
| 型號： | AD9957_07 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 53/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957_07 |
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AD9957
I/O Update Rate Register
Address 0x04, four bytes are assigned to this register. This register is effective without the need for an I/O update.
Rev. 0 | Page 53 of 60
Table 22. Bit Descriptions for I/O Update Rate Register
Bit(s)
Mnemonic
31:0
I/O Update Rate
Description
Ineffective unless CFR2 Bit 23 = 1. This 32-bit number controls the automatic I/O update rate (see the
Automatic I/O Update section); default is 0xFFFFFFFF.
RAM Segment Register 0
Address 0x05, six bytes are assigned to this register. This register is effective without the need for an I/O update. This register is only
active if CFR1 Bit 31 = 1 and there is a Logic 0 to Logic 1 transition on the RT pin.
Table 23. Bit Descriptions for RAM Segment Register 0
Bit(s)
Mnemonic
47:32
RAM Address Step
Rate 0
31:22
RAM End Address 0
21:16
Not Available
15:6
RAM Start Address 0
5:3
Not Available
2:0
RAM Playback Mode 0
Description
This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM
address range.
This 10-bit number identifies the ending address for the RAM state machine.
This 10-bit number identifies the starting address for the RAM state machine.
This 2-bit number identifies the playback mode for the RAM state machine (see Table 6).
RAM Segment Register 1
Address 0x06, six bytes are assigned to this register. This register is only active if CFR1 Bit 31 = 1 and there is a Logic 1 to Logic 0
transition on the RT pin.
Table 24. Bit Descriptions for RAM Segment Register 1
Bit(s)
Mnemonic
47:32
RAM Address Step
Rate 1
31:22
RAM End Address 1
21:16
Not Available
15:6
RAM Start Address 1
5:3
Not Available
2:0
RAM Playback Mode 1
Description
This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM
address range.
This 10-bit number identifies the ending address for the RAM state machine.
This 10-bit number identifies the starting address for the RAM state machine.
This 2-bit number identifies the playback mode for the RAM state machine (see Table 6).
Amplitude Scale Factor Register (ASF)
Address 0x09, four bytes are assigned to this register. This register is only active if CFR1 Bit 9 = 1.
Table 25. Bit Descriptions for ASF Register
Bits
Mnemonic
31:16
Amplitude Ramp Rate
Description
Ineffective unless CFR1 Bit 8 = 1. This 16-bit number controls the rate at which the OSK controller
updates amplitude changes to the DDS.
If CFR1 Bit 8 = 0 and CFR1 Bit 23 = 0, then this 14-bit number is the amplitude scale factor for the DDS.
If CFR1 Bit 8 = 0 and CFR1 Bit 23 = 1, then this 14-bit number is the amplitude scale factor for the DDS
when the OSK pin is Logic 1.
If CFR1 Bit 8 = 1, then this 14-bit number sets a ceiling on the maximum allowable amplitude scale
factor for the DDS.
Ineffective unless CFR1 Bit 8 = 1. This 2-bit number controls the step size for amplitude changes to the
DDS (see Table 10).
15:2
Amplitude Scale Factor
1:0
Amplitude Step Size
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