參數(shù)資料
型號(hào): AD9957_07
廠商: Analog Devices, Inc.
英文描述: 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述: 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC
文件頁(yè)數(shù): 30/60頁(yè)
文件大?。?/td> 840K
代理商: AD9957_07
AD9957
The circled numbers in Figure 44 indicate specific events,
explained as follows:
Rev. 0 | Page 30 of 60
Event 1—an I/O update or profile change activates the RAM
bidirectional ramp mode.
Event 2—the RT pin switches to Logic 1. The state machine
initializes to the start address of RAM Segment Register 0 and
begins incrementing the RAM address counter.
Event 3—the RT pin remained at Logic 1 long enough for the
state machine to reach the end address of RAM Segment
Register 0, at which point the address counter is halted.
Event 4—the RT pin switches to Logic 0. The state machine
initializes to the end address of RAM Segment Register 1, resets
the internal timer, and begins decrementing the RAM address
counter.
Event 5—the RT pin switches to Logic 1. The state machine
initializes to the start address of RAM Segment Register 0,
resets the internal timer, and begins incrementing the RAM
address counter.
Event 6—the RT pin switches to Logic 0. The state machine
initializes to the end address of RAM Segment Register 1, resets
the internal timer, and begins decrementing the RAM address
counter.
Event 7—the RT pin remained at Logic 0 long enough for the
state machine to reach the start address of RAM Segment
Register 1, at which point the address counter is halted.
Event 8—the RT pin switches to Logic 1. The state machine
initializes to the start address of RAM Segment Register 0,
resets the internal timer, and begins incrementing the RAM
address counter.
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