參數(shù)資料
型號: AD9957_07
廠商: Analog Devices, Inc.
英文描述: 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述: 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC
文件頁數(shù): 18/60頁
文件大小: 840K
代理商: AD9957_07
AD9957
INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in the interpolating
DAC mode is shown in Figure 28; grayed items are inactive. In
this mode, the Q data path, DDS, and modulator are all disabled;
only the I data path is active.
Rev. 0 | Page 18 of 60
As in quadrature modulation mode, the PDCLK pin functions
as a clock, synchronizing the input of data to the AD9957.
No modulation takes place in the interpolating DAC mode;
therefore, the spectrum of the data supplied at the parallel port
remains at baseband. However, a sample rate conversion takes
place based on the programmed interpolation rate. The inter-
polation hardware processes the signal, effectively performing
an oversample with a zero-stuffing operation. The original
input spectrum remains intact and the images that otherwise
would occur from the sample rate conversion process are
suppressed by the interpolation signal chain.
0
PDCLK
I/Q IN
E
DAC_RSET
IOUT
IOUT
TxENABLE
DAC GAIN
θ
cos (
ω
t+
θ
)
I
S
F
CLOCK
F
P
8
SYSCLK
PLL
÷2
C
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND CONTROL
AD9957
ω
sin (
ω
t+
θ
)
S
S
P
P
M
2
2
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
18
D
I
Q
IS
QS
B
18
18
16
16
H
F
I
C
C
(
H
F
I
C
C
(
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
FTW
PW
O
R
RAM
P
C
S
SERIAL I/O
PORT
I
PROGRAMMING
REGISTERS
3
2
I Q
IS QS
OUTPUT
SCALE
FACTOR
C
I
S
Figure 28. Interpolating DAC Mode
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