參數(shù)資料
型號: AD9957_07
廠商: Analog Devices, Inc.
英文描述: 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述: 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC
文件頁數(shù): 15/60頁
文件大小: 840K
代理商: AD9957_07
AD9957
MODES OF OPERATION
OVERVIEW
The AD9957 has three basic operating modes
Rev. 0 | Page 15 of 60
ctral images and retaining the original
ion
A detailed block diagram of
The inverse sinc filter is available in all three modes.
Quadrature modulation (QDUC) mode (default)
Interpolating DAC mode
Single tone mode
The active mode is selected via the operating mode bits in
Control Function Register 1 (CFR1). Single tone mode allows
the device to operate as a sinusoidal generator with the DDS
driving the DAC directly.
Interpolating DAC mode bypasses the DDS, allowing the user
to deliver baseband data to the device at a sample rate lower
than that of the DAC. An internal chain of rate interpolation
filters the user data, upsample, to the DAC sample rate. Com-
bined, the filters provide for programmable rate interpolation
while suppressing spe
baseband spectrum.
QDUC mode employs both the DDS and the rate interpolat
filters. In this case, two parallel banks of rate interpolation
filters allow baseband processing of in-phase and quadrature
(I/Q) signals with the DDS providing the carrier signal to be
modulated by the baseband signals.
the AD9957 is shown in Figure 25.
0
PDCLK
I/Q IN
E
DAC_RSET
IOUT
IOUT
TxENABLE
FTW
PW
DAC GAIN
θ
cos (
ω
t+
θ
)
I
S
F
CLOCK
F
P
8
SYSCLK
PLL
÷2
C
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND CONTROL
AD9957
ω
sin (
ω
t+
θ
)
S
S
P
P
M
2
2
2
C
O
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
R
RAM
P
C
I
S
S
SERIAL I/O
PORT
I
PROGRAMMING
REGISTERS
3
I Q
IS QS
18
D
I
Q
IS
QS
B
18
18
16
16
H
F
I
C
C
(
H
F
I
C
C
(
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
OUTPUT
SCALE
FACTOR
Figure 25. Detailed Block Diagram
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