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參數(shù)資料
| 型號： | AD9888KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 100/140/170/205 MSPS Analog Flat Panel Interface |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, MQFP-128 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大小： | 249K |
| 代理商： | AD9888KS-100 |
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REV. A
AD9888
–9–
Sync Processing
The AD9888 contains circuitry that enables it to accept com-
posite sync inputs, such as Sync-on-Green or the trilevel syncs
found in digital TV signals. A complete description of the sync
processing functionality is found in the Sync Slicer and Sync
Separator sections.
Hsync, Vsync Inputs
The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. It is possible to
operate the AD9888 without applying Hsync (using an external
clock, external clamp, and single port output mode) but a number
of features of the chip will be unavailable, so it is recommended
that Hsync be provided. This can be either a sync signal directly
from the graphics source, or a preprocessed TTL or CMOS
level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no ter-
mination is required or desired.
Serial Control Port
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150
series resistors placed between the pull-up resistors and
the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from a
3.3 V power supply (V
DD
). They can also work with a V
DD
as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB Clamping
To digitize the incoming signal properly, the dc offset of the input
must be adjusted to fit the range of the on-board A/D converters.
Most graphics systems produce RGB signals with black at ground
and white at approximately 0.75 V. However, if sync signals are
embedded in the graphics, the sync tip is often at ground and
black is at 300 mV. Then white is at approximately 1.0 V. Some
common RGB line amplifier boxes use emitter-follower buffers
to split signals and increase drive capability. This introduces a
700 mV dc offset to the signal, which must be removed for
proper capture by the AD9888.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In most graphics systems, black is transmitted between active
video lines. Going back to CRT displays, when the electron
beam has completed writing a horizontal line on the screen
(at the right side), the beam is deflected quickly to the left side
of the screen (called horizontal retrace) and a black signal is
provided to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is almost always
a period following Hsync called the back porch where a good
black reference is provided. This is the time when clamping
should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the Clamp Polarity (Register
0Fh, Bit 6).
A simpler method of clamp timing employs the AD9888 inter-
nal clamp timing generator. The Clamp Placement register is
programmed with the number of pixel times that should pass
after the trailing edge of HSYNC before clamping starts. A
second register (Clamp Duration, Register 06h) sets the duration
of the clamp. These are both 8-bit values, providing considerable
flexibility in clamp generation. The clamp timing is referenced
to the trailing edge of Hsync because, though Hsync duration
can vary widely, the back porch (black reference) always follows
Hsync. A good starting point for establishing clamping is to set
the clamp placement to 08h (providing 8 pixel periods for the
graphics signal to stabilize after sync) and set the clamp dura-
tion to 14h (giving the clamp 20 pixel periods to reestablish the
black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value (47 nF)
results in recovering from a step error of 100 mV to within
1/2 LSB in 10 lines with a clamp duration of 20 pixel periods
on a 60 Hz SXGA signal.
YUV Clamping
YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the video signal rather than the bottom. For
these signals it can be necessary to clamp to the midscale range
of the A/D converter range (80h) rather than bottom of the
A/D converter range (00h).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the series bus register. The red
and blue channels each have their own selection bit so that they
can be clamped to either midscale or ground independently. The
clamp controls are located in register 10h and are Bits 1 and 2.
The midscale reference voltage that each A/D converter clamps
to is provided independently on the RMIDSCV and BMIDSCV
pins. These two pins should be bypassed to ground with a
0.1
μ
F capacitor (even if midscale clamping is not required).
Gain and Offset Control
The AD9888 can accommodate input signals with inputs ranging
from 0.5 V to 1.0 V full scale. The full-scale range is set in three
8-bit registers (Red Gain, Green Gain, and Blue Gain; Registers
08h, 09h, and 10h respectively).
Note that
increasing
the gain setting results in an image with
less
contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset; Registers 0Bh, 0Ch, and 0Dh respec-
tively) provide independent settings for each channel.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9888KS-140 | TRI N PLUG F 2-13 |
| AD9888KS-170 | TRI N RECP M FLG 2-13 |
| AD9888KS-205 | TRI N RECP M J/N 2-13 |
| AD9891 | CCD Signal Processors with Precision Timing⑩ Generator |
| AD9895 | CCD Signal Processors with Precision Timing⑩ Generator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9888KS-140 | 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述: |
| AD9888KS-170 | 制造商:Analog Devices 功能描述:ADC Triple 170Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:170MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC |
| AD9888KS-205 | 制造商:Analog Devices 功能描述:ADC Triple 205Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:205MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC |
| AD9888KSZ-100 | 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9888KSZ-140 | 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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