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參數(shù)資料
| 型號(hào)： | AD9888KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 100/140/170/205 MSPS Analog Flat Panel Interface |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, MQFP-128 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AD9888KS-100 |
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REV. A
AD9888
–13–
TIMING
The following timing diagrams show the operation of the AD9888
analog interface in all clock modes. The part establishes timing
by having the sample that corresponds to the pixel digitized
when the leading edge of Hsync occurs sent to the “A” data
port. In dual-channel mode, the next sample is sent to the “B”
port. Future samples are alternated between the “A” and “B”
data ports. In single-channel mode, data is only sent to the “A”
data port, and the “B” port is placed in a high impedance state.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
DATACK
DATACK
DATA
HSOUT
t
PER
t
DCYCLE
t
SKEW
Figure 12. Output Timing
Hsync Timing
Horizontal sync is processed in the AD9888 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360
°
in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9888. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
COAST Timing
In most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Verti-
cal Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-On-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync.
To avoid upsetting the clock generator during Vsync, it is impor-
tant to ignore these distortions. If the pixel clock PLL sees
extraneous pulses, it will attempt to lock to this new frequency,
and will have changed frequency by the end of the Vsync period.
It will then take a few lines of correct Hsync timing to recover at
the beginning of a new frame, resulting in a “tearing” of the
image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9888KS-140 | TRI N PLUG F 2-13 |
| AD9888KS-170 | TRI N RECP M FLG 2-13 |
| AD9888KS-205 | TRI N RECP M J/N 2-13 |
| AD9891 | CCD Signal Processors with Precision Timing⑩ Generator |
| AD9895 | CCD Signal Processors with Precision Timing⑩ Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9888KS-140 | 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述: |
| AD9888KS-170 | 制造商:Analog Devices 功能描述:ADC Triple 170Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:170MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC |
| AD9888KS-205 | 制造商:Analog Devices 功能描述:ADC Triple 205Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:205MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC |
| AD9888KSZ-100 | 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9888KSZ-140 | 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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