參數(shù)資料
型號(hào)： AD9888KS-100
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： 100/140/170/205 MSPS Analog Flat Panel Interface
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： PLASTIC, MQFP-128
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 249K
代理商： AD9888KS-100
REV. A
AD9888
–20–
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00
7-0
Chip Revision
An 8-bit register that represents the silicon revision.
Revision 0 = 0000 0000, Revision 1 = 0000 0001.
PLL DIVIDER CONTROL
01
7-0
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a master clock from an incoming Hsync
signal. The master clock frequency is then divided by an
integer value, such that the output is phase-locked to Hsync.
This PLLDIV value determines the number of pixel times
(pixels plus horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active pixels
in the display.
The 12-bit value of the PLL divider supports divide ratios
from 2 to 4095. The higher the value loaded in this regis-
ter, the higher the resulting clock frequency with respect
to a fixed Hsync frequency.
VESA has established standard timing specifications, which
will assist in determining the value for PLLDIV as a func-
tion of horizontal and vertical display resolution and frame
rate (Table IV).
However, many computer systems do not conform pre-
cisely to the recommendations, and these numbers should
be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9888 updates the full divide ratio only when the
LSBs are changed. Writing to this register by itself will
not trigger an update.
02
7-4
PLL Divide Ratio LSBs
The four least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9888 updates the full divide ratio only when this
register is written to.
CLOCK GENERATOR CONTROL
03
7-6
VCO Range Select
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high fre-
quencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actu-
ally operates at a higher frequency but then divides down
the clock rate afterwards. Table VI shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
Table VI. VCO Ranges
VCORNGE
Pixel Rate Range
00
01
10
11
10–45
45–90
90–150
150+
The power-up default value is 01.
03
5-3
Charge Pump Current
Three bits that establish the current driving the loop filter
in the clock generator.
Table VII. Charge Pump Currents
CURRENT
Current ( A)
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
7-3
Clock Phase Adjust
A five-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25
°
shift
in sampling phase.
The power-up default value is 16.
04
CLAMP TIMING
05
7-0
An 8-bit register that sets the position of the internally
generated clamp.
When the external clamp control bit is set to 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync. The clamp place-
ment may be programmed to any value up to 255, except 0.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
When the external clamp control bit is set to 1, this regis-
ter is ignored.
06
7-0
Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
When the external clamp control bit is set to 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync, and continues for
(Clamp Duration) pixel periods. The clamp duration may
Clamp Placement
相關(guān)PDF資料
PDF描述
AD9888KS-140 TRI N PLUG F 2-13
AD9888KS-170 TRI N RECP M FLG 2-13
AD9888KS-205 TRI N RECP M J/N 2-13
AD9891 CCD Signal Processors with Precision Timing⑩ Generator
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9888KS-140 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:
AD9888KS-170 制造商:Analog Devices 功能描述:ADC Triple 170Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:170MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC
AD9888KS-205 制造商:Analog Devices 功能描述:ADC Triple 205Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:205MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC
AD9888KSZ-100 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD9888KSZ-140 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
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