參數(shù)資料
型號(hào)： AD9888KS-100
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： 100/140/170/205 MSPS Analog Flat Panel Interface
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： PLASTIC, MQFP-128
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 249K
代理商： AD9888KS-100
REV. A
AD9888
–18–
Table V. Control Register Map (continued)
Read and
Write or
Read Only
Hex
Address
Default
Value
Bits
Register Name
Function
0EH
R/
W
7:0
0
*******
Sync Control
Bit 7—Hsync Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 6 in Register 0Eh.)
Bit 6—Hsync Input Polarity. Indicates to the PLL the polarity of the incom-
ing Hsync signal. (Logic 0 = active low, Logic 1 = active high.)
Bit 5—Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync).
Bit 4—Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is selected
via Bit 6 in Register 14H.
Bit 3—Active Hsync select. Logic 0 selects Hsync as the active sync. Logic
1 selects Sync-on-Green as the active sync. Note: the indicated Hsync will
be used only if Bit 4 is set to Logic 1 or if both syncs are active (Bits 1, 7 =
Logic 1 in Register 14H).
Bit 2—Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)
Bit 1—Active Vsync override. If set to Logic 1, the user can select the Vsync
to be used via Bit 0. If set to Logic 0, the active interface is selected via Bit
3 in Register 14H.
Bit 0—Active Vsync select. Logic 0 selects Raw Vsync as the output Vsync.
Logic 1 selects Sync Separated Vsync as the output Vsync. Note: the indi-
cated Vsync will be used only if Bit 1 is set to Logic 1.
Bit 7—Clamp Function. Chooses between Hsync for Clamp signal or an-
other external signal to be used for clamping. (Logic 0 = Hsync, Logic 1 =
Clamp.)
Bit 6—Clamp Polarity. Valid only with external Clamp signal. (Logic 0 =
active high, Logic 1 selects active low.)
Bit 5—COAST select. Logic 0 selects the coast input pin to be used for the
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 4—COAST Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 3 in register 0Fh.)
Bit 3—COAST Polarity. Changes polarity of external COAST signal.
(Logic = 0 = active low, Logic 1 = active high.)
Bit 2—Seek Mode Override. (Logic 1 = allow low-power mode, Logic 0 =
disallow low-power mode.)
Bit 1—
PWRDN
. Full Chip Power Down, active low. (Logic 0 = Full Chip
Power Down, Logic 1 = normal.)
Sync-on-Green Threshold – Sets the voltage level of the Sync-on-Green
slicer’s comparator.
Bit 2—Red Clamp Select – Logic 0 selects clamp to ground. Logic 1 selects
clamp to midscale (voltage at Pin 9).
Bit 1—Blue Clamp Select – Logic 0 selects clamp to ground. Logic 1 selects
clamp to midscale (voltage at Pin 24).
Bit 0—Must be set to 1 for proper operation.
Sync Separator Threshold – Sets how many internal 5 MHz clock periods the
sync separator will count to before toggling high or low. This should be set to
some number greater than the maximum Hsync or equalization pulsewidth.
Pre-COAST – Sets the number of Hsync periods that coast becomes active
prior to Vsync.
Post-COAST – Sets the number of Hsync periods that coast stays active
following Vsync.
*
1
******
**
0
*****
***
0
****
****
0
***
*****
0
**
******
0
*
*******
0
0FH
R/
W
7:1
0
*******
*
1
******
**
0
*****
***
0
****
****
1
***
*****
1
**
******
1
*
10H
R/
W
7:3
01111
***
Sync-on-Green
Threshold
*****
0
**
******
0
*
*******
0
00100000 Sync Separator
Threshold
11H
R/
W
7:0
12H
R/
W
7:0
00000000 Pre-COAST
13H
R/
W
7:0
00000000 Post-COAST
相關(guān)PDF資料
PDF描述
AD9888KS-140 TRI N PLUG F 2-13
AD9888KS-170 TRI N RECP M FLG 2-13
AD9888KS-205 TRI N RECP M J/N 2-13
AD9891 CCD Signal Processors with Precision Timing⑩ Generator
AD9895 CCD Signal Processors with Precision Timing⑩ Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9888KS-140 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:
AD9888KS-170 制造商:Analog Devices 功能描述:ADC Triple 170Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:170MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC
AD9888KS-205 制造商:Analog Devices 功能描述:ADC Triple 205Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:205MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC
AD9888KSZ-100 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱(chēng):568-1854-1
AD9888KSZ-140 功能描述:IC FLAT PANEL INTERFACE 128-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱(chēng):568-1854-1
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