參數(shù)資料
型號(hào)： AD9865BCPRL
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Broadband Modem Mixed-Signal Front End
中文描述： SPECIALTY TELECOM CIRCUIT, QCC64
封裝： MO-220-VMMD, LFCSP-64
文件頁(yè)數(shù)： 27/48頁(yè)
文件大小： 1672K
代理商： AD9865BCPRL
AD9865
TXPGA CONTROL
The AD9865 also contains a digital PGA in the Tx path distri-
buted between the TxDAC and IAMP. The TxPGA is used to
control the peak current from the TxDAC and IAMP over a
7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution.
A 6-bit word is used to set the TxPGA attenuation according to
the mapping shown in Figure 58. The TxDAC gain mapping is
applicable only when Bit 0 of Register 0x0E is set, and only the
four LSBs of the 6-bit gain word are relevant.
Rev. A | Page 27 of 48
0
6-BIT DIGITAL CODE (Decimal Equivalent)
T
0
8
16
24
32
40
48
56
64
0
–20
–16
–17
–18
–19
–14
–15
–12
–13
–10
–11
–8
–9
–6
–7
–2
–3
–4
–5
–1
TxDACs IOUTP OUTPUT
HAS 7.5dB RANGE
IAMPs IOUTN AND IOUTG
OUTPUTS HAS 19.5dB RANGE
Figure 58. Digital Gain Mapping of TxPGA
The TxPGA register can be updated via the PGA[5:0] port or
SPI port. The first method should be considered for fast updates
of the TxPGA register. Its operation is similar to the description
in the RxPGA Control section. The SPI port allows direct up-
date and readback of the TxPGA register via Register 0x0A with
an update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of
Register 0x0A must be set for a read or write operation.
Table 17 lists the SPI registers pertaining to the TxPGA. The
TxPGA control register default setting is for minimum
attenuation (0 dBFS) with the PGA[5:0] port disabled for Tx
gain control.
Table 17. SPI Registers TxPGA Control
Address (Hex)
Bit
0x0A
(6)
(5:0)
0x0B
(6)
(5)
0x0E
(0)
Description
Enable TxPGA update via SPI
TxPGA gain code
Select TxPGA via PGA[5:0]
Select RxPGA via PGA[5:0]
TxDAC output (IAMP disabled)
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