參數(shù)資料
型號(hào)： AD9854AST
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： CMOS 300 MHz Quadrature Complete-DDS
中文描述： PLL FREQUENCY SYNTHESIZER, 200 MHz, PQFP80
封裝： MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 23/44頁(yè)
文件大?。?/td> 433K
代理商： AD9854AST
AD9854
–23–
REV. 0
CLR ACC2
F1
0
F
MODE
TW1
DPW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
Figure 46. Effect of CLR ACC2 in FM Chirp Mode
HOLD
F1
0
F
MODE
TW1
DFW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
F1
DELTA FREQUENCY WORD
RAMP RATE
Figure 47. Illustration of HOLD Function
FM Chirp
Figure 46 graphically illustrates the effect of CLR ACC2 bit upon
the DDS output frequency. Note that reprogramming the registers
while the CLR ACC2 bit is high allows a new FTW1 frequency
and slope to be loaded.
Another function that is available only in the chirp mode is the
HOLD pin, Pin 29. This function will stop the clocking signal to
the ramp rate counter that will, in turn, halt any further clocking
pulses to the frequency accumulator, ACC1. The effect is to
halt the chirp and hold the output frequency in a static condition
at the frequency existing just before HOLD was pulled high.
When the HOLD pin is returned low, the clocks are resumed
and chirp continues. During a hold condition, user may change
the programming registers; however, the ramp rate counter must
resume operation at its previous rate until a count of zero is
obtained before a new ramp rate count can be loaded. Figure 47
illustrates the effect of the hold function on the DDS output
frequency.
Users may utilize the 32-bit automatic I/O Update counter when
constructing complex chirp or ramped FSK sequences. Since
this internal counter is synchronized with the AD9854 System
Clock, it allows precisely timed program changes to be invoked. In
this manner, user is only required to reprogram the desired
registers before the automatic I/O Update pulse is generated.
A complete discussion of this function is presented elsewhere
in this data sheet.
In the chirp mode, the destination frequency is not directly
specified. If the user fails to control the chirp, the DDS will control
itself by naturally confining its output between dc and Nyquist;
however, unless terminated by the user, the chirp will continue
until power is removed.
It is the user’s choice as to what occurs when the chirp destination
frequency is reached. Here are a few of the choices:
1. Stop and hold at the destination frequency using the HOLD
pin, or by loading all zeros into the Delta Frequency Word
registers of the frequency accumulator (ACC1).
相關(guān)PDF資料
PDF描述
AD9856AST CMOS 200 MHz Quadrature Digital Upconverter
AD9856 CMOS 180 MHz Quadrature Digital Upconverter(時(shí)鐘頻率為180MHz,CMOS的積分上變頻器)
AD9857 CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
AD9857AST CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
AD9865 Broadband Modem Mixed-Signal Front End
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9854ASTZ 功能描述:IC DDS QUADRATURE CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9854ASVZ 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80
AD9854PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS
AD9856 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MHz Quadrature Digital Upconverter
AD9856/PCB 制造商:Analog Devices 功能描述:Evaluation Board For Digital Up Converter 56 Pin LFCSP Ep 制造商:Analog Devices 功能描述:DGTL UP CNVRTR 56LFCSP - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*