參數(shù)資料
型號： AD9558BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 96/104頁
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 64LFCSP
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 4:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9558
Rev. B | Page 91 of 104
Table 96. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit
Address
Bits
Bit Name
Description
0x0A07
[7:5]
Reserved
4
History updated
Clears history updated IRQ
3
Frequency unclamped
Clears frequency unclamped IRQ
2
Frequency clamped
Clears frequency clamped IRQ
1
Phase slew unlimited
Clears phase slew unlimited IRQ
0
Phase slew limited
Clears phase slew limited IRQ
Table 97. IRQ Clearing for Reference Inputs
Address
Bits
Bit Name
Description
0x0A08
7
Reserved
6
REFB validated
Clears REFB validated IRQ
5
REFB fault cleared
Clears REFB fault cleared IRQ
4
REFB fault
Clears REFB fault IRQ
3
Reserved
2
REFA validated
Clears REFA validated IRQ
1
REFA fault cleared
Clears REFA fault cleared IRQ
0
REFA fault
Clears REFA fault IRQ
0x0A09
7
Reserved
6
REFD validated
Clears REFD validated IRQ
5
REFD fault cleared
Clears REFD fault cleared IRQ
4
REFD fault
Clears REFD fault IRQ
3
Reserved
2
REFC validated
Clears REFC validated IRQ
1
REFC fault cleared
Clears REFC fault cleared IRQ
0
REFC fault
Clears REFC fault IRQ
Table 98. Incremental Phase Offset Control
Address
Bits
Bit Name
Description
0x0A0A
[7:3]
Reserved
Reserved.
2
Reset phase offset
Resets the incremental phase offset to zero.
This is an autoclearing bit.
1
Decrement phase offset
Decrements the incremental phase offset by the amount specified in the incremental
phase lock offset step size registers (Register 0x0312 to Register 0x0313).
This is an autoclearing bit.
0
Increment phase offset
Increments the incremental phase offset by the amount specified in the incremental
phase lock offset step size registers (Register 0x0312 to Register 0x0313).
This is an autoclearing bit.
Table 99. Reference Validation Override Controls
Address
Bits
Bit Name
Description
0x0A0B
[7:4]
Reserved
Reserved.
3
Force Timeout D
Setting this autoclearing bit emulates timeout of the validation timer for Reference D
and allows the user to make REFD valid immediately.
2
Force Timeout C
Setting this autoclearing bit emulates timeout of the validation timer for Reference C
and allows the user to make REFC valid immediately.
1
Force Timeout B
Setting this autoclearing bit emulates timeout of the validation timer for Reference B
and allows the user to make REFB valid immediately.
0
Force Timeout A
Setting this autoclearing bit emulates timeout of the validation timer for Reference A
and allows the user to make REFA valid immediately.
0x0A0C
[7:4]
Reserved
Reserved.
3
Ref Mon Override D
Overrides the reference monitor REF FAULT signal for Reference D (default: 0).
2
Ref Mon Override C
Overrides the reference monitor REF FAULT signal for Reference C (default: 0).
1
Ref Mon Override B
Overrides the reference monitor REF FAULT signal for Reference B (default: 0).
0
Ref Mon Override A
Overrides the reference monitor REF FAULT signal for Reference A (default: 0).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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